EETimes India - January 1, 2009 - (Page 10)

In Focus | System -level design Sub-100nm tech brings EDA opportunities continued from page Events ICETiC 2009 Jan. 8-10, 2009 Kamraj College of Engineering and Technology, Virudhunagar economics of the fabrication. Interconnect—Second major issue encountered due to scaling of features has been the increasing interconnects delay. The function of interconnect or wiring system is to distribute clock and other signals and to provide power/ground to and among the various circuits/systems functions on a chip. With the continued push to smaller geometries based on the Moore’s law and growing need to improve performance and lower power dissipation in IC, interconnect has become a challenge for feature scaling. Graph shows how the interconnect delay has been rising with smaller scaling vis-à-vis the device delay. In 100nm the device delay was ~20ps and that of the RC delay of the interconnect of 1mm was ~1ps while in the project 35nm technology the device delay will come down to ~1ps but the RC delay of interconnect will be ~250ps. Not only that the power dissipation in interconnect will also increase to ~80 per cent from ~50 per cent in the earlier technology. The increase in the interconnect wire aspect ratio together with decrease in the line-to-line spacing results in the increase in the coupling capacitance, increasing power dissipation which is proportional to the capacitance. Discuss Which fab tech will rule the sub100-nm era? DT_08: My forecast is that nanolithography will make it big in the next few years. What do you think? The increase in interconnect delay is a bottleneck not only to achieve high performance and lower power dissipation in the design but also at the design level the issue of ainterconnect is more profound. The exact layers and the length of interconnect is decided at the layout level prior to which the designer is done with the design both functionally and in term of performance. The timing information at design synthesis is based on a model of interconnect which is difficult to determine accurately because of distributive nature of interconnect and also the coupling capacitance of interconnect which depends on both the spatial locations of the neighbouring wires and temporal relation between the signals on the wire. This can potentially result in iterating back and forth at synthesis and P&R level for timing closure of the chip. This can invalidate the existing interconnect model currently used in the high level designs. The coupling capacitance can also result in crosstalk which can decrease the signal integrity. The global interconnect such as clock, power, ground requires more thorough handling and modelling to decrease delay by adding repeaters which increases the area of the chip. Read the full article to know the EDA methodologies and solutions necessary for migrating to these sub-100nm technologies. This online version explores the complete design flow and the system level, synthesis and P&R tools that could improve designer’s productivity. ■ Topics covered by the International Conference on Emerging Trends in Computing include active networks, AI, agent computing, data and information security, genetic algorithms, multimedia systems, knowledge-based systems, medical informatics, mobile computing, parallel and distributed systems, pattern recognition, and soft computing techniques. Visit website or inquire direct. IMTEX/Tooltech 2009 Jan. 22-28, 2009 Bangalore International Exhibition Centre, Bangalore The exhibition will feature metalcutting machine tools, cutting tools, tool systems, machine tool accessories, metrology, and CAD/ CAM. View website or send an inquiry. ISA Vision Summit 2009 Feb. 16-17, 2009 Hotel Leela Palace, Bangalore ISA Vision Summit 2009 will focus on “unleashing opportunities“ in India as the “gateway to future markets.” There will be sessions on local products, the Indian design influence, volume, embedded software’s influence on hardware, venture capital funding, green energy, as well as international business trends. Inquire now or go to event website. COMPONEX NEPCON 2009 Feb. 24-26, 2009 Pragati Maidan, New Delhi Algorithmic synthesis boosts efficiency continued from page once they are translated to the hardware. By using algorithmic synthesis to create an architectural template, the design architect can get a real performance estimate for each choice that he makes, ensuring that the architecture will meet all the hardware requirements before handing it over for implementation. 2. Define a code application to meet functionality and performance goals. During template creation, the design architect can explore all combinations of streaming interfaces, memories and wires to obtain the best mix for the defined constraints of the design. AS can take any of these combinations and generate RTL which can then be profiled for performance and functionality. 3. Fine-tune the code to meet area and power goals. The template also allows the architect to compare multiple partitioning and data movement Discuss Algorithmic synthesis: the best route to ESL? With its benefits for developing complex designs, algorithmic synthesis is hailed as the best way to achieve broad ESL deployment. Do you agree? 4. Hand off the design for IC integration. Once the template has been simulated and shown to meet design requirements, it is ready for hand off for integration into the IC. During this hand off, the template essentially becomes a functional specification of the hardware to b e b uilt . T he comp lete template can be simulated at the RTL level to ensure that it meets or exceeds the re quire d design p er formance. Read the full ar ticle that demonstrates how to use AS to accelerate design time. It also discusses the other benefits of using AS across the whole IC design process. ■ This exhibition on electronic components, materials and production technology brings together the latest developments and innovative solutions for the industry. Participants will showcase products, do business, network, and discuss industry development for future growth. Go to website or inquire direct. Convergence India 2009 Convergence India is a three-day event that brings the information and communication technology (ICT) sector together, and provides an international platform for creators and implementers of new technologies to form profitable alliances and partnerships. Check out event website or send an inquiry. More eeEvents Mar. 18-20, 2009 Pragati Maidan, New Delhi schemes to identify the best implementation in terms of area, power and performance for any given algorithm. 10 EE Times-India | January 1-15, 2009 | www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/Interconnect.HTM?ClickFromNewsletter_090101 http://forum.eetindia.co.in/FORUM_POST_1000039193_1200098893_0.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090101_ICETiC.htm?ClickFromNewsletter_090101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090101_ICETiC.htm?ClickFromNewsletter_090101 http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013457&eventLocId=1000001417&method=inquiryEnter&eventType=EE?ClickFromNewsletter_090101 http://forum.eetindia.co.in/FORUM_POST_1000039193_1200098893_0.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/signal integrity.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090101_IMTEX.htm?ClickFromNewsletter_090101 http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013464&eventLocId=1000001424&method=inquiryEnter&eventType=EE?ClickFromNewsletter_090101 http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013464&eventLocId=1000001424&method=inquiryEnter&eventType=EE?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800555777_1800000_TA_e770bbe3.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013459&eventLocId=1000001419&method=inquiryEnter&eventType=EE?ClickFromNewsletter_090101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090101_ISA.htm?ClickFromNewsletter_090101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090101_COMPONEX.htm?ClickFromNewsletter_090101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090101_COMPONEX.htm?ClickFromNewsletter_090101 http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013465&eventLocId=1000001425&method=inquiryEnter&eventType=EE?ClickFromNewsletter_090101 http://forum.eetindia.co.in/FORUM_POST_1000039193_1200098906_0.HTM ?ClickFromNewsletter_090101 http://forum.eetindia.co.in/FORUM_POST_1000039193_1200098906_0.HTM ?ClickFromNewsletter_090101 http://www.embeddeddesignindia.co.in/ART_8800556237_2800004_TA_e4ad64a1.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_090101_Convergence.htm?ClickFromNewsletter_090101 http://www.eetindia.co.in/event/inquiry.do?page=eventInquiry&eventId=100013466&eventLocId=1000001426&method=inquiryEnter&eventType=EE?ClickFromNewsletter_090101 http://www.eetindia.co.in/EVENT_DISPLAY_EE.HTM?ClickFromNewsletter_090101 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090101_EETI02.htm?ClickFromNewsletter_090101

Table of Contents Feed for the Digital Edition of EETimes India - January 1, 2009

EETimes India - January 1, 2009 Contents Chip-Package Co-Design Lowers Design Cost National Semiconductor Sub-100nm Tech Brings EDA Opportunities Algorithmic Synthesis Enhances Design Efficiency ICETIC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX�NEPCON 2009, Convergence India 2009

EETimes India - January 1, 2009

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