EETimes India - January 1, 2009 - (Page 4)

Trends Hybrid solutions ease embedded devt continued from page increased debug visibility and improved execution control. Previous-generation chips can be used to develop higher-level software even before specifications are finalised. Depending on how much their register interfaces have changed, they may or may not be applicable for firmware and driver development. First versions of transactionlevel virtual platforms can be made available within six to eight weeks after specifications have stabilised. Customers are able to start development of firmware, drivers and embedded operating systems as early as nine to twelve months prior to silicon. While the accuracy of virtual platforms is a concern, loosely timed (LT) models are sufficient for general software development. They contain accurate register interfaces and functionally correct behaviour, but little or no timing. Software developed on such virtual platforms will run without modification on the final board. However, timing-critical software can only be developed on LT platforms but not verified for timing issues. When RTL is stabilised, embedded software development on hardware prototypes be- comes possible. Most commonly, customers use emulation or FPGA-based hardware prototyping and often bring up software three to six months prior to silicon being available. The hardware prototype accurately reflects the target implementation, making it well-suited for timing-critical sof t ware development. When silicon returns from fabrication, development boards containing the actual chip are the most common development vehicles. Software development now happens on “the real thing,” which significantly contributes to the sof tware developer’s comfort level. However, debugging embedded software at this stage can be cumbersome, both because of lack of control over the execution of the chip as well as the limitations on how to inspect the inside of the chip for debugging purposes. Even though they happen at different stages of a project, the use of these four techniques has been seriously debated on. While verification engineers and some hardware-aware software developers like the accuracy of hardware, other software developers prefer completely virtual development vehicles before RTL is coded. Typical trade-offs among the different solutions include time to market, speed, accuracy, ease of execution control, visibility for debug, and bring-up effort. Do more on EE Times India Ask the author Read related articles • SoC devt in 45nm: Challenges, opportunities for Indian engineers • Emulation wins over FPGA prototyping • System level tools enable complex design solutions Best of both worlds Given the individual strengths of the various approaches, it is time think about hybrid solutions that connect virtual platforms and hardware prototypes using high-speed transactionlevel interfaces (see figure). Many software developers dislike development boards on their desk. They prefer a development environment that combines a keyboard, screen and their favourite software debugger. Using hybrid solutions consisting of virtual platforms and hardware prototypes enables remote access scenarios, in which the user interface of the embedded device and some of its I/O is presented to the software developer as part of the virtual platform. The underlying execution engine becomes a mix of virtual platform and hardware prototype without the user noticing details. For instance, if processors are not available as bond out cores, their execution is often much faster in software using modern ISS technology. Figure: A hybrid approach allows end-to-end prototyping—from pre-RTL virtual platform to hardware prototype. Another issue addressed by hybrid approaches is model availability for virtual platforms. With RTL re-use rates approaching 50 to 60 per cent, pre-existing RTL does not need to be abstracted and modelled again. It can simply be mapped to the hardware protot ype and connected to transactionlevel models representing new functionalit y. The resulting hybrid solution still becomes available early in the project, while the RTL for new functionality is still under development. It takes three technology components to enable hybrid solutions. All of them are available today. Starting on the hardware side, physical interfaces must be provided to connect the actual hardware prototype to the workstation running the simulation. PCI Express is a common solution here. Second, data must be transported using a protocol agreed upon by both software and hardware worlds. SCE-MI has become a standard in this domain. Finally, for conversion from the transaction-level model to the transport interface, transactors are necessary to translate highlevel protocols like AXI, OCP and AMBA. Virtual platforms and hardware prototypes have found adoption in their own right. It is time to declare a truce and let design teams capitalise on the combined advantages of software and hardware-based development methods by using hybrid approaches for early software development. ■ EE Times-India | January 1-15, 2009 | www.eetindia.com http://www.eetindia.co.in/ART_8800551839_1800000_NT_a5e11535.HTM http://www.eetindia.co.in/ART_8800551839_1800000_NT_a5e11535.HTM http://www.eetindia.co.in/ART_8800551839_1800000_NT_a5e11535.HTM http://www.eetindia.co.in/ART_8800497522_1800000_TA_055dcf7a.HTM http://www.eetindia.co.in/ART_8800497522_1800000_TA_055dcf7a.HTM http://www.eetindia.co.in/ART_8800466118_1800000_TA_e3837428.HTM http://www.eetindia.co.in/ART_8800466118_1800000_TA_e3837428.HTM http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/RTL.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/PCI Express.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/OCP.HTM?ClickFromNewsletter_090101 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090101_EETI02.htm?ClickFromNewsletter_090101

Table of Contents Feed for the Digital Edition of EETimes India - January 1, 2009

EETimes India - January 1, 2009 Contents Chip-Package Co-Design Lowers Design Cost National Semiconductor Sub-100nm Tech Brings EDA Opportunities Algorithmic Synthesis Enhances Design Efficiency ICETIC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX�NEPCON 2009, Convergence India 2009

EETimes India - January 1, 2009

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