EETimes India - January 1, 2009 - (Page 5)

Trends Chip-package co-design lowers design cost continued from page needs to make an intelligent arbitration. Figure 1 shows a design example in which the die is being migrated to a new technology and the existing package interface needs to be re-used as much as possible. In this example, the previous package ball assignment can be obtained from a spreadsheet in which the ball assignments on the east and west side of the package are fixed and their interface to the PCB will be reused. The north side of the chip has a fixed interface due to timing constraints. Therefore, the north-side package balls need to be re-assigned in order to honour the fixed chip interface. On the south side, the designer has the freedom to optimise the package ball assignment as well as the chip I/O pad placement. The area highlighted in white has fixed constraints from either the chip or the package. The challenge here is to automatically design the layout of the chip I/O pads, the flip-chip bumps and the package balls while satisfying the fixed constraints in both the chip and the package Figure 1: Example of die migration with fixed package and chip constraints. simultaneously. Without an integrated co-design tool, this can take weeks of manual layout. Any subsequent changes in the chip or package side can require up to several more days of data synchronisation. An integrated chip-package co-design system is designed to handle the package and chip constraints simultaneously. The data synchronisation between the chip and the package is done automatically by its constraint driven I/O placement, bump assignment and package ball as- Figure 2: Resolving package and chip constraints using an integrated chippackage co-design system. signment engines. Figure 2(a) illustrates the design state after initial chip I/O placement without package constraints where the package is not routable given the fixed package balls. Figure 2(b) shows the result after package-driven I/O placement on the east and west sides where the I/O cells are re-placed and bumps are re-assigned to assure routability to the fixed package balls. Figure 2(c) shows the result after chipdriven package ball assignment on the north side, where the package balls are re-assigned to assure routability to the fixed I/O interface on the chip. Figure 2(d) shows the result after the design completion where the tool has automatically optimised the chip I/O placement, bump assignment and package ball assignment on the south side. The constrained automation allows such tasks to be done within minutes and hours instead of days and weeks. Design changes can occur early in the design planning stage and as late as just before the tape-out. Making changes in conventional environments is painful because it requires a lot of manual work. There is also a risk of data inconsistency between the chip and the package. Using a single database, an integrated chip-package co-design solution handles ECOs automatically. A package change is accepted if the change can be propagated down the design hierarchy without breaking the hard design constraints. Both the package and chip layout are updated automatically. Similarly, a chip design change can be propagated up to the package level if it is feasible. When there is a conflict between chip and package constraints, the tool provides a way for the user to arbitrate between the chip and package. Most importantly, since an ECO is handled in an integrated database, it guarantees data consistency between the chip and the package and the built-in data checker assures the design to be layout vs. schematic (LVS) clean. Chip planning used to be done with pencils and papers. But now, taping out a large SoC design requires advanced floor-planning tools. Flip-chip planning is undergoing a similar evolution. A more precise and efficient method of designing the I/O interface is needed, especially for flip-chip designs. This method should allow an early feasibility study and have the power to optimise the package and chip interface design while satisfying the tight constraints imposed by both the chip and the package. Leveraging a chip co-design solution is becoming a differentiating factor in reducing design cost and meeting time-to-market requirements. ■ EE Times-India | January 1-15, 2009 | www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/PCB.HTM?ClickFromNewsletter_090101 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090101_EETI02.htm?ClickFromNewsletter_090101

Table of Contents Feed for the Digital Edition of EETimes India - January 1, 2009

EETimes India - January 1, 2009 Contents Chip-Package Co-Design Lowers Design Cost National Semiconductor Sub-100nm Tech Brings EDA Opportunities Algorithmic Synthesis Enhances Design Efficiency ICETIC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX�NEPCON 2009, Convergence India 2009

EETimes India - January 1, 2009

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