EETimes India - January 1, 2009 - (Page 8)

In Focus | System -level design Use system modelling for AMBA continued from page cent cycle accuracy. The graphical model and simulation analysis was completed in approximately one week. To make the evaluation of the two busses comparable in terms of flow, throughput and latency, the following considerations were adopted: 1. The AHB is a single-channel, shared bus. The AXI is a multichannel, read/write optimised bus. Each bus master, or requesting bus port, connects to the single-channel shared bus in the AHB, while each AXI bus master connects to a Read address channel, Read data channel, Write address chan- nel, Write data channel, and Write response channel. The primary throughput channels for the AXI are the Read/Write data channels, while the address, response channels are to improve pipelining of multiple requests. Assume there are four masters on each bus going to three slaves. The four master ports might include uProcessor, Direct Memory Access (DMA), DSP, USB. The three slaves might include on-chip RAM, off-chip SDRAM, and an APB bus bridge. 2. To approximate the bandwidth of the two busses, one must count the number of read/write channels of the AXI Bus–six for three bus slaves. This suggests that the AHB Bus should support some multiple of bus width and/or speed to match the data throughput. The System Model can vary these combinations with simple parameter changes, however, the AHB bus speed was assumed to be double the AXI Bus, and two times the width. This will make the comparison of the two busses more realistic. 3. To evaluate the efficiency of both busses, different burst sizes were selected; small, medium, and large. Small equates to the width of the AHB Bus, medium equates to two AHB Bus transfers, and large equates to four AHB bus transfers. 4. If the AXI is a 64 bit bus running at 200 Mhz, then the AHB will be a 128 bit bus running at 400 Mhz. The burst sizes will be: small (16 Bytes), medium (32 Bytes), and large (64 Bytes). This paper will focus on the requirements for quick model construction, the attributes to be monitored and workloads to be generated. The design goal is to select the bus that performs best in terms of throughput, Do more on EE Times India Ask the author Read related articles • Choosing the bus for your app • Automate formal verification for OCP • Designing an SPI Figure 1: Block diagram of the bus comparison model. latency, and utilisation for single or multiple channels. The analysis will compare the two bus technologies side by side for 16, 32, and 64 Byte transfers. Average per channel utilisation relates to power consumption. While the AXI Bus has multiple read/write channels to improve performance, and should perform better on average and peak latency measurements; it is not clear by how much due to the concurrency of internal bus transfers. The shared AHB Bus should be utilised more efficiently; it is not clear by how much due to the arbitration algorithm. The System Level Model will provide insights into to both busses, such that a designer could select the right bus for a particular application. For this modelling exercise, we used a standard software application called VisualSim from Mirabilis Design Inc. This is a concept engineering software application that enables exploration of embedded systems for performance and power trade-off. We could create models in VisualSim using the configurable, parameterised library blocks, application-specific functions, standard component generators (processors, memory, caches, bus and switches) and a template-driven SystemC. VisualSim optimises the initial concept through a series of modelling refinements and abstractions to allow the best architecture to become an executable specification. System model overview The AHB bus comparison model is shown in Figure 2 and the AXI bus comparison model is shown Figure 2: VisualSim block diagram of the AHB bus comparison model. continued on page EE Times-India | January 1-15, 2009 | www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/simulation.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800428346_1800004_TA_9a116401.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800534594_1800000_TA_baf16d7f.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800546179_1800004_AN_beffbc28.HTM?ClickFromNewsletter_090101 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090101_EETI02.htm?ClickFromNewsletter_090101 http://www.eetindia.com

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EETimes India - January 1, 2009 Contents Chip-Package Co-Design Lowers Design Cost National Semiconductor Sub-100nm Tech Brings EDA Opportunities Algorithmic Synthesis Enhances Design Efficiency ICETIC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX�NEPCON 2009, Convergence India 2009

EETimes India - January 1, 2009

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