EETimes India - January 1, 2009 - (Page 9)

In Focus | System -level design Use system modelling for AMBA continued from page in Figure 3. The system model consists of the following: 1. uProcessor, DMA, DSP, and USB Master bus ports. 2. AHB, or AXI Bus Arbiter. 3. RAM, SDRAM, and Bridge Slave bus ports. 4. Result plots and window displays for statistics. Modelling results AHB vs. AXI read/write latencies—The AHB Bus latencies start out lower than the AXI Bus at 16 Byte transaction size and the AHB Bus does not exceed the AXI Bus at 64 Byte transaction size. Based on the plot trends, one can estimate that the AXI Bus should have lower latencies above 128Byte transaction sizes, by changing the Transaction_Size_Bytes parameter and rerunning the model. AHB vs. AXI throughput—The throughput plots are identical, which is expected if both have the same source traffic rates and sizes. AHB vs. AXI utilisation—The AHB Bus utilisation is higher than the AXI Bus channels for all transaction sizes, which is expected since the AXI Bus has six channels. The percentage values for Bus master parameters uProcessor Master Speed Mhz = 400.0 Bus Command = Read Bus Rate = 32.0 / Speed Mhz Speed Mhz = 400.0 Bus Command = Write Bus Rate = 64.0 / Speed Mhz Speed Mhz = 400.0 Bus Command = Write Bus Rate = 64.0 / Speed Mhz Speed Mhz = 400.0 Bus Command = Read Bus Rate = 64.0 / Speed Mhz Processor Width = 64 Bits Bus Transaction Size = 16, 32, 64 Bytes Bus Destination = RAM DMA Width = 64 Bits Bus Transaction Size = 16, 32, 64 Bytes Bus Destination = SDRAM DSP Width = 64 Bits Bus Transaction Size = 16, 32, 64 Bytes Bus Destination = Bridge Bus Rate = 64.0 / Speed Mhz Bus Transaction Size = 16, 32, 64 Bytes Bus Destination = SDRAM Figure 3: VisualSim block fiagram of the AXI Bus comparison model. the AXI Bus do not track the AHB Bus, since it is running at one-half the speed, width of the AHB Bus. Analysis VisualSim was able to provide the necessary plots to compare the two busses. The latency plots show that the AHB bus can provide comparable, or lower, latencies up to 64 Byte transaction sizes. The AHB Bus is running at twice the speed, double the width. The throughputs are the same, given the same traffic sources. The utilisations are higher for the AHB Bus, as the AXI Bus has six read/write channels. In terms of power, the single AHB should be approximately 4X a single AXI Bus channel, given the speed and width. Since there are six AXI Bus channels, plus some additional channels, the AXI Bus should consume approximately 1.5X the power of the AHB Bus. Design impacts As a result of this bus model comparison, some bus design considerations emerge: 1. Consider the peak utilisation of a bus channel. If the model shows the peak loading is in the 70 per cent to 80 per cent range, then the bus can sustain additional traffic without redesign. 2. Consider the peak latency for a critical path, such as uProcessor to RAM. Will the peak latency allow the design to meet its overall timing objectives, such as a video frame rate? 3. Consider the power consumption of the bus topology. Can a shared bus reduce power consumption? Results The AHB Bus performed best for the given traffic rates and sizes. The AXI Bus was rated higher for throughput, even though the comparison was the same for both models, since it has additional capacity. The AXI Bus would use approximately 50 per cent more power, assuming similar process technology, again giving the edge to the AHB Bus. ■ DMA Master DSP Master USB Master Bus arbiter parameters AHB Bus AXI Bus Bus master parameters RAM Slave SDRAM Slave Bridge Slave Speed Mhz = 200.0 Speed Mhz = 200.0 Speed Mhz = 400.0 RAM Width = 64 Bits SDRAM Width = 64 Bits Bridge Width = 64 Bits Speed Mhz = 400.0 Speed Mhz = 200.0 Bus Width = 128 Bits Bus Width = 64 Bits EE Times-India | January 1-15, 2009 | www.eetindia.com http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090101_EETI02.htm?ClickFromNewsletter_090101 http://www.eetindia.com

Table of Contents Feed for the Digital Edition of EETimes India - January 1, 2009

EETimes India - January 1, 2009 Contents Chip-Package Co-Design Lowers Design Cost National Semiconductor Sub-100nm Tech Brings EDA Opportunities Algorithmic Synthesis Enhances Design Efficiency ICETIC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX�NEPCON 2009, Convergence India 2009

EETimes India - January 1, 2009

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