Project Analog - February 2008 - (Page 16) driver is reduced by half at the cost of two additional pins. This method is employed in the ADC14DS105, a 14-bit converter capable of sampling data up to 105 Msamples/s. The eye diagram for one of the output drivers (see Fig. 1) is shown with the driver running at close to its maximum rate of 1,120 Mbit/s. This approach is scalable. Once the total bandwidth requirements exhaust the capabilities of even the dual data-lane approach, additional data lanes can be added to further reduce the bandwidth load placed on any single output driver. The question of how to get a serial data output ADC to communicate with a parallel processor can be tackled with the addition of a functional block, specifically, a deserializer block. While some standalone chips can execute the function, it is entirely plausible to include this function into the FPGA used as the digital receiver. Many FPGA manufacturers include this standard function in their fig. 1 adcs such as thE 14-bit adc14ds105, add a sEcond data signal so thE bandwidth rEquirEd of Each lvds drivEr is rEducEd by half at thE cost of two additional Pins. toolbox. National Semiconductor has code available for the Xilinx Virtex-4 platform that it distributes free of charge. Similarly, many DSPs are beginning to include data input structures that will accept highspeed serial data and deserialize the data internally. As for ASICs, including a deserializer block in the next revision would be a relatively simple matter that should not significantly contribute to the overall die size. True, challenges exist to employing a high-speed serial data interface for transmitting data from the ADC to the receiver. But for those applications with the flexibility to employ some additional functional blocks, the rewards may be great. The ability to deliver simultaneously on the often times competing goals of higher converter speed, greater converter resolution, and smaller physical layout sizes is indeed valuable enough to make it worth consideration. Contents Viewpoint Digital potentiometer application circuits Smart ADC architecture Layout techniques for high accuracy and resolution ADCs Analog news speed serial LVDS data interfaces. Fortunately, these challenges are already understood and adequate strategies have been developed to mitigate these negatives. Specifically, there is a speed limitation to LVDS drivers. A 14-bit converter running at 105 Msample/s would require a bit stream at 1,470 Mbits/s. Even a well designed LVDS driver cannot be expected to reliably work much beyond 1,100 Mbit/s, at least not over any meaningful trace length. Another problem is more architectural in nature. Typically, an ADC samples signals, converts them into digital representations, and then sends this data to a 16 · ProjeCT ANALog · feb 08 processor (an FPGA, a DSP, or in some cases an ASIC). With some notable exceptions, almost all digital processors are parallel in nature. There is a fundamental discrepancy between the format of the data coming out of the ADC and the expected nature of the data at the receiver. The speed question is not trivial. Without addressing it, ADCs with serial data interfaces would be limited in conversion rate, resolution, or possibly even both. However, using multiple data lanes is one method that avoids this limitation. By adding a second data signal, the bandwidth required of each LVDS Microchip analog page Mixed-signal overview Sample center microchipDIRECT Reference designs/ app notes Technical training • http://www.microchip.com http://www.microchip.com/analog http://www.microchip.com/analog http://www.microchip.com/mixedsignal http://sample.microchip.com/Default.aspx?testCookies=true http://www.microchipdirect.com/catalogselection.aspx?returnURL=default.aspx http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1469&filter1=function&redirects=appnotes http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1469&filter1=function&redirects=appnotes http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1423
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