Project Analog - February 2008 - (Page 19) Architecture Pushes Limits of SAr ADCs By Christina Nickolas Contents Viewpoint Digital potentiometer application circuits Smart ADC architecture a chargEsharing sar adc (a) rEPorts an fom of 65fj/ convErsion-stEP by using PassivE chargE-sharing tEchniquEs. a diE micrograPh (b) of thE chargEsharing sar adc imPlEmEntEd in 90-nm digital cmos. A t the recent International SolidState Circuits Conference, a team of engineers at IMEC (Leuven, Belgium) demonstrated a 9-bit 50-Msamples/s A/D converter architecture with a record figure-of-merit of 65 fJ per conversion—2.5 times better than the best A/D converter (ADC) ever reported and five times better than state-of-the-art ADCs designed for nomadic applications. (Nomadic applications such as software-defined radio analog-frontends, however, require high-accuracy high-speed ADCs at very low power consumption.) Traditionally, 8 to 10bit ADCs operating at several tens of megasamples per second have for a long time been the territory of pipeline architectures. The team proposed an SAR architecture that uses passive charge sharing (instead of active charge redis19 · ProjeCT ANALog · feb 08 tribution) to both sample the input signal and perform the binary-scaled feedback during the successive approximation. The architecture works completely in the charge domain. The input is sampled on a capacitor, and during the SAR algorithm, charge is added or subtracted (using simple passive switches) until the result converges to zero. The only active element in the ADC is the comparator, which is basically why the lowest power consumption limit could be achieved. The comparator doesn’t consume any power during inactive mode so the power consumption of the ADC scales linearly with the sampling frequency. To avoid needing a high-speed clock (and its associated power consumption), an asynchronous controller is also used. Implemented in 90-nm Layout techniques for high accuracy and resolution ADCs Analog news digital CMOS, the chip measures 1.2 x 1.1 mm2, of which 400 x 200 µm2 is used by the ADC core. In tests, silicon measurements showed a power consumption of 0.7 mW at 50 Msamples/s. Measured INL and DNL were below 0.6 LSB. Fully digital implementation of the ADC needs only MOS switches and metal-oxide-metal capacitors— making the ADC scalable toward the 45-nm node and beyond. For more information, call Katrien Marent of IMEC Corporate Communications at 011.321.628.1880, e-mail katrien.marent@imec.be, or visit www.imec.be. Microchip analog page Mixed-signal overview Sample center microchipDIRECT Reference designs/ app notes Technical training • http://www.microchip.com http://www.microchip.com/analog http://www.microchip.com/analog http://www.microchip.com/mixedsignal http://sample.microchip.com/Default.aspx?testCookies=true http://www.microchipdirect.com/catalogselection.aspx?returnURL=default.aspx http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1469&filter1=function&redirects=appnotes http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1469&filter1=function&redirects=appnotes http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1423 http://www.imec.be
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