IEEE Circuits and Systems Magazine - Q1 2018 - 22
The hardware complexities (in terms of FA + FF) of the
above-mentioned algorithms are compared to those of
both the fully-pipelined and the non-pipelined versions
of the factored interpolated cascade structure (Fig. 10).
The bound in Fig. 11 indicates that there may still be
room for considerable improvement in the hardware
complexity. This could justify further effort in identifying even more efficient filter structures that would realize the target specification for Example 3. The question
is, how close can a practical design get to this boundary?
We again believe that the presented illustration and
boundary in Fig. 11 should provide a valuable insight
regarding how efficient a new filter structure might be
in realizing this order-120 filter.
Example 4: Order-100 wideband FIR filter [53]:
As our final high-order wideband filter-design example,
we now consider another demanding FIR filter, referred
to as filter "B" in [53], with the following specifications:
■ Passband edge ~ p = 0.2r rad.; Stopband edge
~ s = 0.24r rad.;
■ Ripple d p = 0.01 (±0.0864 dB); Attenuation d s = 0.01
(-40 dB);
In [53] this filter was examined using four transposed
direct-form implementations, and compared using
45
40
1,000
3330
Remez Coefficients [53]
LMS 1983 [45]
3039
3051
2892
2950
FIRGAM 2008 [53]
PMILP 2002 [54], [55]
50
2777
2472
Non-Pipelined
Factored Cascade 2014 [46], [47]
55
Two-Stage Cascade 2011 [51]
Single-Stage 2011 [50]
MILP Method 2011 [49], [50]
2044
Fully-Pipelined
Factored Cascade 2017 [58]
62
60
Fully-Pipelined
Factored Cascade 2014 [46], [47]
1872
Fig. 8
Non-Pipelined
Factored Cascade 2017 [58]
Given a required min(δp, δs) = 0.001,
our analysis suggests that it is
70 practically unlikely to be able to
realize a direct-form FIR filter
that corresponds to the left of
65 the boundary.
2682
Achievable Remez Order as a Function of FA + FF When Target min(δp, δs) = 0.001 (Attenuation = 60 dB)
75
Max Remez Order that Can Be Practically Realized
filter coefficients obtained with: the FIRGAM method
[53], the Trellis algorithm [59], the Remez method
[11]-[13] and Li's SPT method [60]. The corresponding hardware complexities are reported in [53] using
an 8-bit input signal (including sign bit). However, we
believe that given the 40-dB attenuation desired in
the stopband of the signal, its wordlength should be
at least 9-bit (including the sign bit) in order to have
the minimum level of resolution that would practically
justify the need for 40-dB attenuation. Given the minor difference in the filter's total hardware complexity, between the 8-bit and 9-bit input cases, we have
used the 8-bit hardware complexities from [53] in
Fig. 12. The bound in (12), shown by the blue solid line
min ^d p, d s h = 0.01, predicts that a practical implementation of this order-100 FIR filter requires a minimum
of approximately 1890 flip-flops and full adders for this
wideband FIR filter. The Fig. 12 gray area indicates the
region that is predicted to be practically unreachable
(especially the denser gray areas) when the target is
min ^d p, d s h = 0.01. A comparison of the four implementations with the bound (11), as illustrated in Fig. 12,
shows that there is considerable room for improvement in its hardware complexity. (Who's going to be
first? Have at it ...!)
1,500
2,000
2,500
3,000
Total Number of Full Adders and Flip-Flops (Hardware Budget in Terms of FA + FF)
Figure 9. Highest attainable remez order (y-axis) of a practically realizable fIr filter based on the bound defined in (12) (using
a = 1), shown by the blue solid line, given a specific hardware budget in terms of the total number of full adders and flip-flops
(x-axis) for the Example-2 filter design case where min ^d p, d sh = 0.001. this plot predicts that when a 60-db stopband attenuation
of the input is required, then achieving a remez order of higher than 62 is quite unlikely if the total hardware budget is less than
1580 fA + ff.
22
IEEE cIrcuIts ANd systEMs MAgAzINE
fIrst quArtEr 2018
Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q1 2018
Contents
IEEE Circuits and Systems Magazine - Q1 2018 - Cover1
IEEE Circuits and Systems Magazine - Q1 2018 - Cover2
IEEE Circuits and Systems Magazine - Q1 2018 - Contents
IEEE Circuits and Systems Magazine - Q1 2018 - 2
IEEE Circuits and Systems Magazine - Q1 2018 - 3
IEEE Circuits and Systems Magazine - Q1 2018 - 4
IEEE Circuits and Systems Magazine - Q1 2018 - 5
IEEE Circuits and Systems Magazine - Q1 2018 - 6
IEEE Circuits and Systems Magazine - Q1 2018 - 7
IEEE Circuits and Systems Magazine - Q1 2018 - 8
IEEE Circuits and Systems Magazine - Q1 2018 - 9
IEEE Circuits and Systems Magazine - Q1 2018 - 10
IEEE Circuits and Systems Magazine - Q1 2018 - 11
IEEE Circuits and Systems Magazine - Q1 2018 - 12
IEEE Circuits and Systems Magazine - Q1 2018 - 13
IEEE Circuits and Systems Magazine - Q1 2018 - 14
IEEE Circuits and Systems Magazine - Q1 2018 - 15
IEEE Circuits and Systems Magazine - Q1 2018 - 16
IEEE Circuits and Systems Magazine - Q1 2018 - 17
IEEE Circuits and Systems Magazine - Q1 2018 - 18
IEEE Circuits and Systems Magazine - Q1 2018 - 19
IEEE Circuits and Systems Magazine - Q1 2018 - 20
IEEE Circuits and Systems Magazine - Q1 2018 - 21
IEEE Circuits and Systems Magazine - Q1 2018 - 22
IEEE Circuits and Systems Magazine - Q1 2018 - 23
IEEE Circuits and Systems Magazine - Q1 2018 - 24
IEEE Circuits and Systems Magazine - Q1 2018 - 25
IEEE Circuits and Systems Magazine - Q1 2018 - 26
IEEE Circuits and Systems Magazine - Q1 2018 - 27
IEEE Circuits and Systems Magazine - Q1 2018 - 28
IEEE Circuits and Systems Magazine - Q1 2018 - 29
IEEE Circuits and Systems Magazine - Q1 2018 - 30
IEEE Circuits and Systems Magazine - Q1 2018 - 31
IEEE Circuits and Systems Magazine - Q1 2018 - 32
IEEE Circuits and Systems Magazine - Q1 2018 - 33
IEEE Circuits and Systems Magazine - Q1 2018 - 34
IEEE Circuits and Systems Magazine - Q1 2018 - 35
IEEE Circuits and Systems Magazine - Q1 2018 - 36
IEEE Circuits and Systems Magazine - Q1 2018 - 37
IEEE Circuits and Systems Magazine - Q1 2018 - 38
IEEE Circuits and Systems Magazine - Q1 2018 - 39
IEEE Circuits and Systems Magazine - Q1 2018 - 40
IEEE Circuits and Systems Magazine - Q1 2018 - 41
IEEE Circuits and Systems Magazine - Q1 2018 - 42
IEEE Circuits and Systems Magazine - Q1 2018 - 43
IEEE Circuits and Systems Magazine - Q1 2018 - 44
IEEE Circuits and Systems Magazine - Q1 2018 - Cover3
IEEE Circuits and Systems Magazine - Q1 2018 - Cover4
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2023Q3
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2023Q2
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2023Q1
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2022Q4
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2022Q3
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2022Q2
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2022Q1
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2021Q4
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2021q3
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2021q2
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2021q1
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2020q4
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2020q3
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2020q2
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2020q1
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2019q4
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2019q3
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2019q2
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2019q1
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2018q4
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2018q3
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2018q2
https://www.nxtbook.com/nxtbooks/ieee/circuitsandsystems_2018q1
https://www.nxtbookmedia.com