IEEE Circuits and Systems Magazine - Q1 2018 - 26

Number of Shift-Adds Needed to Implement a Given Remez Order (log Scale)
103

1,081-Order
Narrowband
Red Line is Fitted 2 ae X
390-Order
Narrowband

Remez Order (log Scale)

Impractical Region?

120

59

35

- 1b

382-Order
Wideband

120-Order
Wideband

120-Order
Narrowband

102

0.36

Samueli
CSD

Conventional Design Border

59-Order
Narrowband
RRS

15
101

0

50

100
150
200
250
Number of Shift-Adds Needed in Specific Implementation

300

350

Figure 14. An empirical approximation of the maximum remez order of an fIr filter (that can be practically realized), given a
number of shift-add operations (adder budget).

to store or communicate one symbol in a message), there
is no clear practical definition of entropy for FIR filters. An
early example of such an attempt is presented in [61].
Based on the ideas presented in the present paper, however, we believe a simple practical definition for the entropy
of an FIR filter is the ratio of the total number of full-adders
and flip-flops (FA + FF) to the minimum Remez order (the
number of zeros in the z-plane) that is needed to satisfy
the desired filter specification. Effectively, FIR entropy is
the average number of FA + FF required to implement each
transfer function zero of the minimum-order Remez filter
in a minimal-hardware FIR filter realization (given a filter
specification).
Hence we postulate that a better understanding or
definition of FIR filter entropy can be acquired through
a more detailed theoretical analysis of the information
associated with the zeros of the transfer function (e.g.,
refer to [46]-[47].)
Should we perhaps define the hardware complexity of
an FIR filter on the basis of the minimum number of transistors required (instead of the number of FA + FF )?
26

IEEE cIrcuIts ANd systEMs MAgAzINE

Any practical flip-flop or full-adder structure is built
using a limited number of transistors and hence it is
quite possible to describe filter complexity by converting the total required FA + FF into a total number of transistors. Nonetheless, we believe such abstraction is not
a suitable way to describe complexity, due to the loss of
information regarding the types of functionalities (add
vs. store) when expressing filter HW complexity in term
of number of transistors. Another relevant concern is
that, of course, a next-generation of integrated nanoscale or atomic-scale structures for full-adders and flipflops may not be based on transistors (i.e., transistors
might be replaced by new devices, e.g., carbon nanotubes) and hence we believe that a definition of complexity at the full-adder and flip-flop functionality level
is more suitable.
V. Conclusion
In this paper, we have investigated a guideline (a measure of goodness) for the required approximate lowest
hardware complexity level for designing FIR filters, and
fIrst quArtEr 2018



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