1997 ACE400 (0.8 µm) 22 × 20 B&W Cells 27.5 Cells/mm2 Pixel Memory: 4 B&W Program Memory: 8 Templates 15.8 GOPS IO: 22 Lines Binary 2002 CACE1k (0.35 µm) 2000 64 × 64 Gray-Scale Cells 82 cells/mm2 Pixel Memory: 4 B&W + 4G ACE4k (0.5 µm) Program Memory: 32 Templates + 64 Dig. Instructions 40 GOPS IO: 16 bit B&W Bus + 2002 16 Lines G Bus 128 × 128 Gray-Scale Cells 180 cells/mm2 ACE16k (0.35 µm) Pixel Memory: 2 B&W + 8G Program Memory: 32 Templates + + 4,096 Dig. Instructions 190 GOPS IO: 32 bit Digital Bus Embedded Data Converters 2004 per Column 128 × 128 Gray-Scale Cells . . . Power Distribution Correction Power Management ACE16k-v2 (0.35 µm) 2005 CACE2 (0.35 µm) ... Sensor Adaptation Loop Based on Retina Principles Eye-RIS (0.18 µm) 2008 176 × 144 Gray-Scale Cells Pixel Pitch 35 µm General-Purpose Embedded 32-bit RISC Processor Multiple Interfaces Per Column ADC - bit First Worldwide VSoC Machine Vision Applications ANAFOCUS 2006 LVC (0.35 µm) 2009 200 × 1 Linear Sensor Pixel Pitch 10.9 µm Standard Ind. Interfaces Five Correlation Outputs Optical Encoding Applic. 150 × 100 Gray-Scale Cells Pixel Pitch 35 µm 88 dB IntraFrame DR Per Pixel ADC-7 bit Automotive Applications 2010 FPOD200 TVHC (0.35 µm) 2010 176 × 144 Gray-Scale Cells Pixel Pitch 33 µm Embedded Prog. Resistive Grid Generation of Multi-Scales Surveillance Applications 32 × 32 Gray-Scale Cells 82 cells/mm2 Pixel Memory: 4 B&W + 4G Program Memory: 32 Templates + 64 Dig. Instructions 470 GOPS IO: 16 bit B&W Bus + 16 Lines G Bus Two Layer Architecture Retina Function Emulation FLIP-Q 176 × 144 Gray-Scale Cells Pixel Pitch 32 µm 146 dB IntraFrame DR Histogram-Based Tone Mapping Per Pixel ADC-7 bit Automotive Applications 2012 1/2 Frame Buffer 2013 320 × 240 Gray-Scale Cells Pixel Pitch 19 µm Block-Wise HDR, Integral Image OpenVX Functionalities Feature Extraction, Surveillance FLIPQ-II 176 × 120 Pixels (Sensing and Gauss. Pyr.) 1/2 Frame Buffer 176 × 120 Gray-Scale Cells Pixel Pitch 44 µm Embedded Prog. SC Grid Generation of Multi-Scales Feature Extraction Figure 7. roadmap of vision chips with cnnum architecture designed at the vision lab of Institute of microelectronics of seville (the bottom-right one was designed in collaboration with cItIus-universidad de santiago de compostela). 100 IEEE cIrcuIts and systEms magazInE sEcOnd quartEr 2018