IEEE Circuits and Systems Magazine - Q2 2018 - 63

-0.7
-0.8
vm / V

-0.9
-1

-1.1
-1.2
-1.3
-1.4

2

w0 = 1.9 nm
w0 = 1.8 nm
w0 = 1.7 nm
w0 = 1.6 nm

1.6

w/nm

w0 = 1.5 nm

1.4

w0 = 1.4 nm
w0 = 1.3 nm

1.2

w0 = 1.2 nm
10-30

10-20
t /s
(a)

10-10

1

100

0.2

0.3

0.4

0.5

0.3

0.4

0.5

1.5 Decreasing w0
w0 = 1.9 nm
1

w0 = 1.3 nm
w0 = 1.4 nm
w0 = 1.5 nm
w0 = 1.6 nm
w0 = 1.7 nm
w0 = 1.8 nm
w0 = 1.9 nm
10-20
t /s
(b)

0.5
0

-0.5
-1
10-10

100

Figure 19. time waveform of the tunnel barrier length w (a) and
of the memristor voltage v m (b) in response to a negative dc
input current I m = - 700 μa for initial memristor states within
the set defined as w 0 ! " 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 , nm.

The Pickett's mathematical description predicts the
emergence of fading memory in the titanium oxide nano-device also under AC periodic stimuli. For example, inserting
a sine wave current of the form i m = itm · sin (2 · r · f · t) with
amplitude itm = 800 μA and frequency f = 10 Hz through the
memristor, the memory state loses the information embedded in its initial condition-swept within the set of values
defined as w 0 ! " 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 , nm -
within the first input cycle, approaching a unique steadystate oscillatory solution, as shown in Fig. 20(a). Depending upon the initial condition, the voltage across the
nano-device, depicted in Fig. 20(b), experiences distinct
transitory behaviours, which all lead, however, to a common steady state solution.
Let us now focus on Wei Lu's mathematical model of
an amorphous silicon-based nanoscale memristor [16].
The analysis of the Wei Lu DAE set will reveal that also
this resistance switching non-volatile memory is affected by the input-induced memory loss phenomenon.
C. The Amorphous Silicon Resistance Switching
Memory from the University of Michigan
The physical structure of a non-volatile resistance
switching memory [23] fabricated at the University of
sEcOnd quartEr 2018

w0 = 1.2 nm
w0 = 1.1 nm
0
0.1

t /s
(a)

w0 = 1.2 nm

10-30

w0 = 1.9 nm
w0 = 1.8 nm
w0 = 1.7 nm
w0 = 1.6 nm
w0 = 1.5 nm
w0 = 1.4 nm
w0 = 1.3 nm

1.8

vm / V

w/nm

1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1

0

w0 = 1.1 nm
0.1

0.2
t /s
(b)

Figure 20. time waveforms of the tunnel barrier length w
and of the nano-device voltage v m in response to a sine
wave input current of the form i m = ti m · sin (2 · r · f · t) with
amplitude ti m = 800 μa and frequency f = 10 Hz for the
set of initial conditions on the memory state expressed by
w 0 ! " 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 , nm. due to lack of
space, in plot (b) only the top and bottom curves are labelled
with their initial conditions, but the value for w 0 associated
to the other curves may be inferred from the aforementioned
set, given that it decreases monotonically along the direction
of the arrow pointing towards south-east.

Michigan is shown in Fig. 21 [16]. The active material
for resistance switching is amorphous silicon, while the
electrodes are made up of silver (Ag) and p-doped polysilicon (p-Si).
The nano-device, stretching over a total length w, is
typically used in combination with a series resistor R s,
which limits the current flow through the memristor,
thus preventing its irreversible physical damage. The
resulting two-terminal circuit element, typically known
as one resistor-one memristor (1R1M) structure and
schematically shown in Fig. 22, is still a memristor [1].
Denoting with l the longitudinal extension of the switching filament within the nano-device, the memory state
T
of the nano-device is defined as x = ^l w h, and may
thus assume values in [0, 1] only. Using symbols v m, M
and v m to represent the voltage drops across the nanodevice and the 1R1M structure, respectively, given that
the current through the overall two-terminal element is
denoted as i m, the DAE set of the nanoscale memristor
is expressed by
IEEE cIrcuIts and systEms magazInE

63



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