IEEE Circuits and Systems Magazine - Q2 2018 - 65

0.6

1010

10-5
Vm = 0.1 V
0

0.2

0.2

0.6

0.8

1

10-5

x
(a)
-105

Vm = -3 V
Vm = -4 V
0

0.2

0.4

10-1

100

0.6

x0 = 0.15 x0 = 0.1

2

x0 = 0.05
x0 = 0.2

x0 = 0.01

1
0.8

1

0
10-5

x
(b)

numerically for each value of the state x within its existence domain the voltage v m, M across the nanoscale device via equation (35), and then using this numerical result to determine the corresponding value for the state
rate of change xo from equation (32). The DRM of the Wei
Lu model for the 1R1M structure is respectively captured
in plots (a) and (b) of Fig. 23 under a number of positive
and negative DC values for the voltage stimulus applied
across the series one-port, specifically for input modulus lying in the set Vm ! {0.1, 0.5, 1, 2, 3, 4} V. Irrespective
of the initial condition, any positive (negative) DC stimulus will inevitably lead the memory state towards the upper (lower) bound, as expected for a real-world memristor. The constant positive (negative) sign of the state rate
xo throughout its existence domain under any positive
(negative) DC input is at the origin for the emergence of
DC fading memory in the 1R1M structure. This is demonstrated in Fig. 24 (25), showing the time waveforms of
the memory state x-plot (a)-of the voltage v m, M falling

10-4

10-3

10-2

10-1

100

t /s
(b)
100
80
x0 = 0.15

60
im /µA

Figure 23. drm of the Wei Lu model for the 1r1m structure
of Fig. 22 under a set of positive (a) and negative (b) dc
values for the input voltage Vm . With reference to plot (a),
the state rate xo goes to infinity at x = 1. this does not represent an issue in numerical simulations, where the state is
not allowed to exceed the upper unitary bound, but calls for
the necessity to reformulate this model in the future. under
a given negative input-refer to plot (b)-the state rate xo at
x = 0 drops suddenly from the respective value indicated
by a white-filled circle to 0 s -1, since the lower state bound
represents an equilibrium for the state equation (32) under
negative inputs.

sEcOnd quartEr 2018

10-2

3

Vm = -2 V

vm ,M /V

.
x/s

-10-15

10-3

4

Vm = -0.1 V

-100

-10-10

10-4

t /s
(a)

Vm = -1 V Vm = -0.5 V

-105

x0 = 0.01

0

Vm = 0.5 V

0.4

x0 = 0.05
x0 = 0.2

x

.
x/s

Vm = 3 V
Vm = 2 V
Vm = 1 V

100

10-10

0.4

Vm = 4 V

105

x0 = 0.15 x0 = 0.1

x0 = 0.1
x0 = 0.05

40
20

x0 = 0.2
x0 = 0.01

0
-20
10-5

10-4

10-3

10-2

10-1

100

t /s
(c)
Figure 24. Evidence for dc fading memory in the 1r1m structure. response to a positive voltage Vm = + 3.13 V. state (a),
voltage v m, M (b), and current i m (c) over time for initial conditions within the set defined as x 0 ! " 0.01, 0.05, 0.1, 0.15, 0.2 , .

across the nano-device-plot (b)-and of the current
i m flowing through the 1R1M structure-plot (c)-in
response to the application of a DC voltage source of
value Vm = 3.13 V ^Vm = - 3 V h across the series one-port
for the set of initial states x 0 ! {0.01, 0.05, 0.1, 0.15, 0.2}
^ x 0 ! {0.65, 0.75, 0.85, 0.95} h .
Since the state evolution function depends upon the
input polarity, the switching kinetics of the 1R1M structure are asymmetric, as may be realized by inspecting
Fig. 23. This is at the origin of the AC fading memory capability of the series one-port of Fig. 22. To give some evidence for the emergence of AC memory loss in the 1R1M
structure, plots (a), (b), and (c) in Fig. 26 respectively
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