IEEE Circuits and Systems Magazine - Q2 2018 - 83

SECOND quartEr 2018

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(iii) Budapest, Hungary, and (iv) Manchester, UK. Among (one processor per pixel), it turned out that in the digithem, the Seville team designed the largest number tal domain, the coarse grid (e.g. 64 pixel per processor)
of chips, and three of them represents important mile- architecture is more efficient. Therefore the Xenon chip
stones. The first of it is the ACE400 (designed in 0.8 µm [27] contained an 8 # 8 sized, locally interconnected
technology) [16], which could handle relatively small SIMD processor array, with an 8 bit digital processors
binary images only, however it could perform ultra- in each node. The Xenon chip was more accurate and
high rate visual decision making, as it was discussed versatile compared to the analog counterparts, and it
above. The second important member of this family is even reached the same speed and power consumption
the 128 # 128 sized ACE16k [20] with high speed opti- figures, however its optical input was implemented on
cal input and grayscale processing. This chip was suc- an additional semiconductor layer, which made the fabcessfully introduced to the industry in the Bi-i system. rication very expensive. Digital CNN emulator circuits
This chip was the last one, which actually implemented were also designed by this team. These are described in
an approximation of the original CNN equations (1) in the next chapter.
the continuous domain. As it turned out, the continuously operating analog multipliers consumes large siliVI. Emulated Digital CNNs
con space, and high power, moreover, their accuracy is As CNN architecture developed and the application opnot satisfactory (3-4 bits). The chip was implemented portunities extended, newer and newer CNN structures
1.5 cm2, with 0.35 µm technology, and it consumed 3 W, were proposed and found to be useful in practice. Howwhich required very special cooling.
ever, desktop based simulators were not able to calTherefore, the next chip of this family, the Q-Eye [22] culate the extended CNN structures with appropriate
applied discrete time analog computation, which turned speed, and available chips did not necessary have the
out to be much more accurate (7 bit), and consumes a appropriate accuracy. To bridge these gaps, emulated
fraction of the power only (20 mW). This latest 176 # 144 digital CNN architectures were proposed and designed.
sized chip, implemented on 180 nm technology, is com- The implementation targets were digital custom ASIC
mercially available in Smart Pixel Sensor (SPS02) [3] in- [28] and FPGA [29]-[31].
dustrial camera produced by Toshiba Teli. This finger
One of the most significant emulated digital CNN
sized vision system can produce above 10,000 complex ASIC development project was the CASTLE project. The
visual decision in a second.
CASTLE architecture [28] was based on a 2 # 3 emuThe Finnish chip family members [18], [23], [24] are lated digital CNN processor array. It was designed and
not very large as to their array size, however they intro- implemented on AMS 0.35 µ CMOS technology with produced several advanced local pixel manipulation func- grammable accuracy and with a 1 ns/virtual CNN cell/
tionalities, like grayscale morphology, pixel-by-pixel ADC and DAC,
rank order filtering, and anisotropic diffusion.
The chips designed at ManchesLastline
ter University [25], [26] are discrete
PR_11
PR_21
PR_31
time analog processor arrays. Therefore, they were always in leading position from accuracy and power efficiency point of views. These chips
introduced asynchronous logic first,
PR_12
PR_22
PR_32
which enabled the implementation
of propagating type morphological
operation (e.g. grassfire) with subnanosecond time constant. The
fastest application (100,000 FPS )
Control Signals
was also reached with one of these
Timing and Control
chip [26].
The Budapest team designed
Reset
Start
Halt ph1 ph2
digital implementation of the CNN
chips. While the previously introFigure 9. a 2 x 3 array of CaStLE processors.
duced chips were fine-grid arrays
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