Pixel Array Vertical Addressing Image Interface Digital Output Digital Image Processing Clock Generation Column S&H clk_ext Analogue References Sensor Control Control Interface Column ADCs Digital Serializer Configuration Registers (a) Lens Column Amplifiers PLL clk_ext Analogue References Control Interface Power Data Interface Control Interface Sensor Control Pixel Array Memory Bank Image Interface Data Processing Image Processor ADC Digital Image Sensor Chip Camera Control Block (b) Image Processing Escene Camera Data-Intensive Processing Math-Intensive Processing Data Bus Control Bus Controller (µP) Communication Ports Vision System Memories (c) Figure 1. conceptual block diagrams for an imager (top), a camera (mid) and an embedded vision system (bottom). the trend is towards full integration of these systems. Progresses in semiconductor technologies, heterogeneous integration and packaging enable compact implementations of these systems in the form of systems-on-chip and/or system-in-Package. 92 IEEE cIrcuIts and systEms magazInE sEcOnd quartEr 2018