IEEE Circuits and Systems Magazine - Q3 2018 - 19

to achieve a symmetric incremental resistance curve. The
resistance was claimed to be almost constant when the
voltage across it changed. In addition, a MOS-bipolar device, which is a drain-gate shorted MOSFET, has also been
proposed for implementing large resistances. Using a
PMOSFET as an example, with negative voltage, it functions
as a diode-connected PMOSFET; with positive voltage, the
parasitic BJT is turned on and works as a diode-connected
BJT. [78] employed this technique to design a circuit with a
low cutoff frequency. Two MOS-bipolar devices connected
in series were used to reduce the distortion of large output
signals, as shown in Fig. 19(c). The cutoff frequency of the
amplifier was 0.025 Hz, in which the equivalent resistance
of the device was larger than 10 13 X [75]. However, standard MOS-bipolar pseudo resistors suffer from process,
voltage, and temperature (PVT) variations in addition to
possible light and EMI sensitivities, leading to variations in
cutoff frequency.
2) Switched capacitors
Switched capacitors can be used to implement on-chip
PVT-insensitive high resistance as shown in Fig. 20(a)
[79]. In this topology, the switching frequency fs and the
capacitor in the middle determine the resistance precisely
as 1/fs C . The switched-capacitor resistor in Fig. 20(b) mitigates manufacturability and interference issues by realizing a tenfold resistance increase by charge sharing in the
switched-capacitor circuits [80]. Unfortunately, the switching produces additional noise along with the weak analog
signal in the front end, decreasing the receiver sensitivity.
3) Miller capacitance multiplier
A Miller capacitance multiplier is used to implement a
large effective capacitance value using a small value capacitor [81], [82]. A two-stage Miller capacitance multiplier for compensation is proposed to implement the high
equivalent capacitance required for an ultra-low frequency biomedical amplifier [81]. In [83], using a capacitance
multiplier, the TIA achieves a passband gain of 89 dBV,
a DC current rejection ranging from 0.5 to 85 n A, and a
23 dB high pass cutoff frequency of 0.5 to 9.5 Hz. This
corresponds to an improvement of six times the DC current rejection range compared with previous techniques
[83]. The current through C m1 is converted to voltage by
R b, amplified and fed back to node Y, as shown in Fig. 21.
The equivalent capacitance seen from node Y can be expressed as follows:
g mcn 1 rox g mcn 2 R b A v2
· C m 1,
C eq =
1 + sC m1 R b

VB
VA

(9)

(a)

(b)

Figure 20. (a) switched-capacitor implementation [79], (b)
switched capacitor implementation with 10-times larger effective resistance than (a) [80].

Vin

r01
-Av1

Vout

-Av2

VDD
Two-Stage
Miller
Capacitance
Multiplier

MX4

MY4

MY3

Vb3

MX3

Vb2

Rm2 Cm2 X
r0x

r0y
MY2

MX2

MCN2

Vb1

Cm1
Vb

MCN1
GND

Figure 21. schematic diagram of two-stage Miller capacitance multiplier [83].

Rf
Vb1

M1
Vb2

A disadvantage of such capacitance multiplication
techniques is the limited linear range they possess, which
is inversely proportional to the multiplication ratio.
ThIrD qUArTEr 2018

4) a -block
To design a filter architecture with an ultra-low cutoff frequency, robust performance and compactness, activeRC implementations are preferred. The architecture of
the first order current-steering low-pass filter (CS-LPF)
is given in Fig. 22, and the a -block is enclosed within the

Vout

+
M2

Vref

α-Block
Figure 22. schematic of Cs-LPF [73].

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