MENTOR / VERIFICATIONHORIZONS

Verification Horizons - February 2011

Sun, 27 Feb 2011 20:58:45 -0500

Your digital edition of Verification Horizons - February 2011 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Verification Horizons - February 2011
- Contents
- SystemVerilog Testbench Acceleration with Co-Emulation
- A Methodology for Hardware-Assisted Acceleration of OVM and UVM Testbenches
- Improving Embedded Software Integration with Veloce Emulation and the Questa Codelink Debug Environment
- UVM:The Next Generation in Verification Methodology
- Achieving Flawless UVM Testbench Creation
- SystemVerilog Boot Camp
- How Transactions Viewing Accelerates Debug of Asynchronous SystemVerilog Designs
- Lessons in Developing and Deploying OVM Compliant VIP
- A Full Function Verilog PLL Logic Model
- Document Driven Verification (DDV): Ready to Throw Out Your Verification Plan?

Verification Horizons - November 2010

Mon, 29 Nov 2010 15:53:58 -0500

Your digital edition of Verification Horizons - November 2010 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Verification Horizons - November 2010
- Table of Contents
- Survey Says: Verification Planning
- Firmware Verification Using Systemverilog Ovm
- A Systemverilog Configurable Coverage Model in an Ovm Setup
- Advanced Techniques for Axi Bus Fabric Verification
- Converting Module-Based Verification Environments to Class-Based Using Systemverilog Oop
- Verifying a Cofluent Systemc Ip Model From a Systemverilog Uvm Testbench in Mentor Graphics Questa
- What You Need to Know About Dead-Code and X-Semantic Checks

Verification Horizons - February 2010

Thu, 18 Feb 2010 19:37:27 -0500

Your digital edition of Verification Horizons - February 2010 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Verification Horizons - February 2010
- Contents
- Using inFact with OVM Sequences
- A Strong Foundation for Design, Verification, and Firmware Requires an Automation Tool for Register Management
- Transaction-Based Testbench Methods Speed Veloce Hardware Acceleration
- Verification Management Eases Those Re-Spin Worries
- What’s New with the Verification Academy?
- Reuse in the Real World—Proving the Accellera VIP Interoperability Kit
- Converting from VMM to OVM: A Case Study
- Agile Transformation in IC Development

Verification Horizons - December 2009

Thu, 03 Dec 2009 11:20:15 -0500

Your digital edition of Verification Horizons - December 2009 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Verification Horizons - December 2009
- Contents
- Evolving Your Organization's ABV Capabilities
- Advanced Static Verification is Indispensible
- Evolving the Coverage-Driven Verification Flow
- Verification of an Ethernet PHY DUT Using Questa MVC
- Breaking Your Own Code; A Design Engineer's Perspective on Verification Using Questa and OVM
- SystemVerilog FrameWorksTM Scoreboard: An Open Source Implementation Using OVM
- SEmulation: Use Your Emulation Board as a Hardware Accelerator for ModelSim SE
- Coding Concise SystemVerilog Assertions
- Methodology for Board Level Functional Simulation and Hardware/Software Co-Verification Using Seamless

Verification Horizons - Q2 2009

Thu, 23 Jul 2009 08:47:26 -0400

Your digital edition of Verification Horizons - Q2 2009 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Verification Horizons - Q2 2009
- Contents
- Verification Teamwork Requires Process Automation
- Team-Driven OVM Testbench Creation
- Evolving Verification Capabilities
- The Dynamic Duo of Veloce and TBX
- Maximizing Your Verification Throughput
- Applying Scalable Verification Components to a USB2.0 HUB
- Porting a Legacy Verification Environment for a Wireless SoC to OVM
- Process Improvements Using OVM Registers and IDesignSpec
- Interface-Based OVM Environment Automation
- Consultants Corner

Verification Horizons - Quarter 1, 2009

Wed, 25 Mar 2009 09:26:01 -0400

Your digital edition of Verification Horizons - Quarter 1, 2009 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Verification Horizons - Quarter 1, 2009
- Contents
- Achieving Higher Quality Design through Questa
- Reduce the Risk of Expensive Post Silicon Debug
- Mitigate Multi-Processor Synchronization Risks with Processor-Driven Verification
- Reusing Legacy VMM VIP in OVM Environments
- A Practical Guide to OVM—Part 3
- Are You in a “bind” with Advanced Verification?

Verification Horizons - Quarter 3, 2008

Fri, 10 Oct 2008 08:54:34 -0400

Your digital edition of Verification Horizons - Quarter 3, 2008 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Verification Horizons - Quarter 3, 2008
- Table of Contents
- A Quick Tour Through OVM 2.0
- Using inFact in an OVM Environment
- Does Your RTL Simulation Accurately Predict the Behavior of Your Silicon
- Understanding and Debugging the Verification Environment
- Processor Driven Verification - Use it for More Than Just Sign-off
- The Innovation Behind Veloce: Time for a Closer Look
- Bringing Everyone on Board with OVM
- A Practical Guide to OVM – Part 2
- Closed Loop Requirement Verification
- Concurrent Verification: Resolving Conflicting Goals
- Automated Register Abstraction Coming to an OVM near You
- Off to the Races with MVCs

Verification Horizons - 1st Quarter, 2008

Fri, 15 Feb 2008 12:57:03 -0500

Your digital edition of Verification Horizons - 1st Quarter, 2008 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Verification Horizons - 1st Quarter, 2008
- Contents
- OVM: Open, Interoperable Verification
- Intelligent Testbench Automation— Now a Reality, No Longer Just a Promise
- Are You Missing Assertions?
- Debugging Synchronization Failures in Multi-Core Designs
- FPGA Design and Verification in Mechatronic Applications
- Migrating Ethernet VIP to OVM Is a Cinch

Verification Horizons - 4th Quarter, 2007

Tue, 23 Oct 2007 12:29:36 -0400

Your digital edition of Verification Horizons - 4th Quarter, 2007 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Verification Horizons - Quarter 4, 2007
- Table of Contents
- Introducing the Open Verification Methodology (OVM)
- Closing the Loop in Testbech Automation
- Power Aware Verification Flow
- Transactional Level Reuse Made Possible by Microcontroller Based BFMs—Extending Your Verification Environment Reuse from Module-Level Verification to Silicon Validation
- Need a Methodology? Don’t Reinvent the Wheel
- Improving Verification Methodology for DO-254 Designs
- Formal Analysis Targets Coverage Goals

Verification Horizons - 2nd Quarter, 2007

Thu, 31 May 2007 09:37:46 -0400

Your digital edition of Verification Horizons - 2nd Quarter, 2007 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Clock Domain Crossing
- Complex Clock Modeling
- Advancing the AVM
- Processor Driven Testbenches
- Solving the Verification IP Re-Use Paradox
- Bringing Visibility to Verification Management
- Article Updates
- Verification for Companies Large and Small
- Denali VIP + Mentor AVM

Verification Horizons - 1st Quarter, 2007

Thu, 15 Feb 2007 13:48:56 -0500

Your digital edition of Verification Horizons - 1st Quarter, 2007 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Table of Contents
- SystemVerilog NOW! And System Verilog for the Future! It Just Keeps Getting Better!
- Improving Design Productivity Through Process Adoption
- Mentor IPD and O-In: Joint Effort Develops VIP for SATA Host and Device Controller Product
- The Second Productivity Revolution: Algorithmic Testbench Synthesis
- The Consultants Corner: Tribal Knowledge

Verification Horizons - 3rd Quarter, 2006

Mon, 25 Sep 2006 07:50:32 -0400

Your digital edition of Verification Horizons - 3rd Quarter, 2006 is available now. Clicking on the Table of Contents will deliver you directly to that page of your issue. Thank you for reading!

- Contents
- The AVM Advantage: Busting the Myth of VMM
- AMCC Standardizes on Questa, SystemVerilog and AVM...
- A Classy Solution to AVM Assertion Usage
- IP Re-use is for Verification IP, not just Silicon, IP
- it's a Matter of Style - SystemVerilog for the e User