Evaluation Engineering - December 2008 - (Page 22)

C-V MEASUREMENTS MOSC A P CV S weep 4200-CVU 4.0E-9 3.0E-9 2.0E-9 1.0E-9 Accumulation Depletion Inversion DCV_OB Figure 2. DC Bias Sweep of MOSCAP Structure Obtained During C-V Testing used to characterize threshold voltages and other parameters during reliability and basic device testing and to model the performance of these devices. The Physics of Semiconductor Capacitance A MOSCAP structure is a fundamental device formed during semiconductor fabrication (Figure 1). Although these devices may be used in actual circuits, they typically are integrated into fabrication processes as test structures. Since they are simple structures and fabrication is easy to control, they are a convenient way to evaluate the underlying processes. The metal/polysilicon layer shown in Figure 1 is one plate of the capacitor, and silicon dioxide is the insulator. Since the substrate below the insulating layer is a semiconducting material, it is not by itself the other plate of the capacitor. In effect, the majority charge carriers become the other plate. Physically, capacitance (C) is determined from the variables in the following equation: C = A (k/d) where: A = area of the capacitor k = dielectric constant of the insulator d = separation of the two plates As a result, the larger A and k are and the thinner the insulator is, the higher the capacitance will be. Typically, semiconductor capacitance values range from nanofarads to picofarads or smaller. The procedure for taking C-V measurements involves the application of DC bias voltages across the capacitor while making the measurements with an AC signal (Figure 1). Commonly, AC frequencies from about 10 kHz to 10 MHz are used for these measurements. The bias is applied as a DC voltage sweep that drives the MOSCAP structure from its accumulation region into the depletion region and then into inversion (Figure 2). A strong DC bias causes majority carriers in the substrate to accumulate near the insulator interface. Since they can’t get through the insulating layer, capacitance is at a maximum in the accumulation region as the charges stack up near that interface because d is at a minimum (Figure 1). One of the fundamental parameters that can be derived from C-V accumulation measurements is the silicon dioxide thickness. As the bias voltage decreases, majority carriers get pushed away from the oxide interface, and the depletion region forms. When the bias voltage is reversed, charge carriers move the greatest distance from the oxide layer, and capacitance is at a minimum because d is at a maximum. From this inversion region capacitance, the number of majority carriers can be derived. The same basic concepts apHCUR Cp_G3 -3.DE+0 -2.DE+0 -1.DE+0 0.DE+0 10 mV to 100 mV AC Source 1.DE+0 HPOT + 30 VDC AC Voltmeter Zx LPOT AC Ammeter LCUR DUT Current Figure 3. Basic Test Setup for C-V Measurements 2 2 • E E • December 2008 www.e v al u a ti o n e n g i n e e r i n g . c o m http://www.evaluationengineering.com

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Evaluation Engineering - December 2008 Contents Editorial Product Briefing Test Software C-V Measurements Nanoelectronics Test Product Guide Company Guide Machine Vision EMC Test Index of Advertisers

Evaluation Engineering - December 2008

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