Circuits Assembly - April 2008 - (Page 22)

Component Packaging Design and Modeling of High-Speed, HighDensity 3-D CSPs and Memory Modules By Frank Y. Yuan, Ph.D., and Richard Crisp Challenges and technologies of high-speed memory systems. DR2 pushed memory clock frequencies to 400 MHz and data rates to 800 Mbps. DDR3 further pushes clock frequencies to 800 MHz, while DDR4 is up to 1.6 GHz. New packaging technologies such as die stacking and package-on-package (PoP) are being developed as well. Here, we demonstrate the design, electrical modeling and testing of a high-speed, high-density DDR2 DIMM module using stacked packages. We designed and modeled a single metal layer DDR2 package, known as Micro Pin Interconnect Layer (µPILR). Next, we evaluated the electrical performance (including power and ground distribution networks) of a four high packageon-package (PoP) stack of µPILR CSPs using detailed 3-D modeling and extraction. Then, this PoP electrical model was used to design an 8 GB DDR2 DIMM. We combined the PoP model with a DIMM connector model and PCB interconnects models to form the complete channel link model. Pre-layout timing and signal simulation results were used to guide the DIMM design. The completed DIMM was Figure 1. Layout of a single substrate µPILR CSP DRAM. thoroughly simulated and Figure 2. Cross-section of the four-height stacked DRAM package. D analyzed to ensure the timing and signal integrity requirements before release to manufacturing. To further explore opportunities for applying the novel packaging to meet projected future needs for DDR3 and DDR4 data rates, we extended our modeling research using the above methodology to look at even higher clock frequencies and data rates. Results show that wire-bonded µPILR PoP stacks are capable of handling data rates of 4 Gbps and higher. A test platform was built to study and measure the memory interconnects topologies at higher frequencies and also validate the software simulation results. We then looked at limitations associated with multiple slot, multiple DIMM configurations. Limiting the Slot Number There are many technical challenges for building high-speed, high-density memory modules. Signal and power integrity are crucial factors that must be modeled and analyzed carefully in the design process, as they influence memory operating speed and electrical performance. High-speed I/O buffers must use low voltages, and have low switching noises, low input/output capacitances and good on-die termination. System topology and configuration affect the overall bus speed due to stub and loading effects. A single slot configuration can operate at a very high speed, yet is limited in capacity, while a four-slot configuration circuitsassembly.com 22 Circuits Assembly APRIL 2008 http://circuitsassembly.com

Table of Contents Feed for the Digital Edition of Circuits Assembly - April 2008

Circuits Assembly - April 2008 Contents Caveat Lector Industry News Market Watch Talking Heads Screen Printing Better Manufacturing Design and Modeling of High-Speed, High-Density 3-D CSPs and Memory Modules The ‘Big Brush Off’ Revisited Impact of Soldering Atmosphere on Solder Joint Formation Beyond Moore’s Law ESD Control For Class 0 ESDS Devices Growing Your Brand This Year’s Model Tech Tips Reflow Soldering Process Doctor Pb-Free Lessons Learned Getting Lean Equipment Advances Apex Product Preview Ad Index Assembly Insider Technical Abstracts

Circuits Assembly - April 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.