Circuits Assembly - April 2008 - (Page 24)

Component Packaging Figure 4. Power and ground connections in a stacked novel package vs. commercial standard BGA. Figure 3. 3-D view of the four-height stacked DRAM package. Figure 5. Schematics of clock distribution net in pre-layout simulation. would significantly reduce operating speed but increase memory capacity. A solution is to limit the slot number (to two or fewer) while increasing the module capacity to achieve higher speed and density at the system level. This requires a solution that can stack two, four and even eight dice in the same form factor with better high-speed performance at comparable costs and manufacturing infrastructure. We found the novel PoP stacking for DRAM significantly increases the memory density within a single package footprint, thus increasing the total DIMM capacity, while maintaining good signal integrity for higher frequency operation. This is an electrically superior topology compared to multiple DIMM slots with the same total system memory. In a stacked DRAM configuration, multiple dice can be active simultaneously, drawing larger current and potentially generating larger power and ground noises. To overcome this possible limitation, the package’s fine pin pitch permits higher I/O pin density and the addition of pins for power and ground nets to reduce power and ground inductance. A µPILR PoP solution permits single die/layer testability, resulting in high package and assembly yields. 3-D CSP Design A wirebond µPILR package was designed for a 1Gb 800MHz DDR2 die. This package used a single metal substrate with FR-4 material, a pin pitch of 0.5 mm and a copper pin height of 125 µm (Figure 1). Special attention was focused on critical nets and the power and ground nets. The differential clock and strobe nets are routed as co-planar lines with 65 impedance, and are well 24 Circuits Assembly APRIL 2008 separated by power and ground from other signal nets. Wide trace and semi-planes are used for power and ground nets. The single substrate packages are then stacked to form a four-high stacked µPILR PoP for high-density DDR2 application (Figure 2 and Figure 3). To accurately and fully evaluate the electrical performance of the package at very high speed, a full 3-D electromagnetic model extraction was carried out. The complete details of the 3-D package, including various package materials and conductors, were incorporated into an Ansoft 3-D solver. Package RLC parameters were calculated for different traces, as well as power and ground nets. A multiport equivalent circuit representing the entire package was obtained. This modeling process enabled evaluation of the package design’s electrical characteristics and performance, and use of the equivalent circuit as a building block for overall total system design and simulation. As stated, power integrity is critical in the stacked package since all four dice can be active simultaneously. The transient current and power to ground loop inductances mostly determine the power/ground switching noises, as indicated by Eq. 1. dV = L di/dt (Eq. 1) To calculate the power to ground inductance, the 3-D power and ground connections in the package, including the bond wire, substrate metal and stacking pins were modeled (Figure 4). The power and ground inductances for the novel package are 1.48nH and 1.50nH, respectively, and for the standard BGA 2.89nH and 1.95nH, respectively. The novel package significantly improved the overall power integrity. circuitsassembly.com http://circuitsassembly.com

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Circuits Assembly - April 2008 Contents Caveat Lector Industry News Market Watch Talking Heads Screen Printing Better Manufacturing Design and Modeling of High-Speed, High-Density 3-D CSPs and Memory Modules The ‘Big Brush Off’ Revisited Impact of Soldering Atmosphere on Solder Joint Formation Beyond Moore’s Law ESD Control For Class 0 ESDS Devices Growing Your Brand This Year’s Model Tech Tips Reflow Soldering Process Doctor Pb-Free Lessons Learned Getting Lean Equipment Advances Apex Product Preview Ad Index Assembly Insider Technical Abstracts

Circuits Assembly - April 2008

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