Circuits Assembly - April 2008 - (Page 26)

Component Packaging Figure 6. Simulated clock signal waveform. Figure 8. CKE net signal waveform. Figure 7. CKE net trace layout. After design, modeling and optimization, the four-stacked novel package was used in the design and build of a highdensity, high-speed 8GB DDR2 DIMM module. The RDIMM was designed based on a modified JEDEC Raw Card M configuration. The DIMM board is double-sided with nine stacked novel DRAM packages on each side, and complies with standard form factor. As a result of a high routing density and tight trace length matching requirements, a buildup 14-layer FR-4 PCB was chosen. This enabled stripline routing with good controlled impedance and separation for high-speed nets. The two top and two bottom layers used laser-drilled microvias for fan-out of the 0.5 mm pitch package pin field. Accurate modeling and comprehensive simulation for timing and signal integrity are essential for such complex, high-speed DDR3/DDR4 Memory Systems system design. A simulation platform was built using HSPICE To explore future application of the novel PoP for DDR3 and and Ansoft Designer. Both SPICE and IBIS driver/receiver modDDR4, we extended the modeling and simulation methodolels were obtained for the DRAM die, register and memory controller. A total link channel model was constructed with DRAM ogy to study the package and interconnect structures at even I/O, the novel PILR package, DIMM board via and traces, DIMM higher speeds. Also, a hardware test platform with the same connector, main board PCB traces and the memory controller package and I/O. Prelayout topology explorations were done for the critical clocks, DQS, DQ and address/control nets to generate layout guidelines and routing Figure 9. Measured eye-diagram (a) and simulated eye-diagram (b) of a single slot point-to-point connection channel in read operation. rules, and to quantify timing requirements in terms of trace length and loading condition. Figure 5 shows the schematics of clock distribution net in our pre-layout simulation. Figure 6 shows a typical clock signal waveform. Notice in the four-stacked design, there are quadruple clock drivers/receivers on the same net vs. a regular single package design. The increased loads slowed down the clock edge, thus changing the timing skew. Also, the multiple branches produce more signal reflections and require careful optimization of the termination resistors through simulation. Identical simulation analyses were applied to other critical nets. After board layout was performed according to the guidelines, a post-layout simulation was carried out to verify the design in the real physical structure. The actual link topology, including trace geometry, layer stack-up and vias, was extracted and then simulated. For example, Figure 7 shows the actual CKE net trace layout, and Figure 8 shows the corresponding signal waveform. Finally, the 8GB DIMM test vehicle was built and tested successfully. This proved the novel PoP’s capability for stacked DDR2 high-speed, high-density memory application. 26 Circuits Assembly APRIL 2008 circuitsassembly.com http://circuitsassembly.com

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Circuits Assembly - April 2008 Contents Caveat Lector Industry News Market Watch Talking Heads Screen Printing Better Manufacturing Design and Modeling of High-Speed, High-Density 3-D CSPs and Memory Modules The ‘Big Brush Off’ Revisited Impact of Soldering Atmosphere on Solder Joint Formation Beyond Moore’s Law ESD Control For Class 0 ESDS Devices Growing Your Brand This Year’s Model Tech Tips Reflow Soldering Process Doctor Pb-Free Lessons Learned Getting Lean Equipment Advances Apex Product Preview Ad Index Assembly Insider Technical Abstracts

Circuits Assembly - April 2008

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