Circuits Assembly - April 2008 - (Page 48)

Packaging Developments Simplest WLCSP structure WLCSP with Cu post and resin mold Embedded device in polymer dielectric Opto WLCSP with Beam Lead High-Capacity Memory Processor Figure 5. Integrated passive network with integrated passive devices and thin-film buildup passive elements (source: Fraunhofer-IZM). IPD embedded silicon substrate Buildup substrate through wafer level fabrication Stacked devices with TSV Embedded Wafer Level Package Figure 4. Examples of wafer-level packaging innovations. nents (e.g., passives, MEMS, optical and even bio components) into a single package. The long-term vision for SiP is the optimized heterogeneous integration of wireless, optical, fluidic, bio elements/interfaces, as well as integrated shielding and heat sinks. This goal requires new materials and control of their interactions on the micrometer and nanometer scale. Numerous concepts for 3-D SiP packaging are emerging, driven largely by the demands of portable consumer products. One of the most important is wafer-level packaging. WLP is an emerging technology, used for both single-chip packaging and SiP, where all elements of a package are within the boundary of the die and all packaging processes performed prior to wafer singulation into individual circuits. WLP development was motivated by the recognition that WLP technology (i.e., parallel processing on the wafer) addresses the need to increase performance and functionality, while reducing system size, power and cost. WLP technology with and without a redistribution layer (RDL) is used for a variety of products where the small size, thickness and weight are important product differentiators. This technology will provide significant cost reductions as it matures and production volume increases. The combination of WLP and wafer/die stacking approaches leads to a large number of variations in WLP technology used for SiP. The highest levels of integration are achieved through 3-D packaging. Die stacking has been used for consumer products, such as cellphones, for several years, with wire bonding used to connect the stacks to the package substrates. An important new technology is through-silicon vias, which allow more efficient die stacking and 3-D integration. These developments lead to more complex packages for both single and multi-die WLPs (Figure 4). The use of TSV as a base for SiP requires solutions for both the thermal density associated with a “cube” of transistors (rather than the planar array of traditional CMOS) and the incorporation of passive devices required for system-level integration. Prototypes have been developed addressing both requirements. Microfluidic components with a form factor suitable for lamination into a device stack with TSV interconnect have been fabricated. Passive networks have also been fabricated that are compatible with TSV interconnected die stacks (Figure 5). Innovations in SiP and WLP technologies depend on the integration of progress in materials and equipment made in all segments of the industry. The successful integration of all of these elements provides a rich portfolio of capabilities in the era of “more Moore” (continued CMOS scaling) and “more than Moore” (the addition of functional diversification). Some of the advanced packaging elements include: • New materials such as nanoparticles to lower processing temperatures and nanotubes for improved thermal and electrical conductivity. • High-density, low-cost packaging substrates. • Wafer thinning, singulation and handling. • Embedded and integrated passives and actives. • Co-design tools. • Equipment for advanced packaging. Innovations in SiP have been accelerating, as this technology becomes a major enabler for a large class of products in the consumer-driven marketplace. Many issues remain that require continued research and development. Today we have not proven the reliability of package-level system integration for complex systems; we do not have a proven strategy for repair and rework of SiP-based products; and we have not resolved the test access and test contactor challenges associated with the high frequency of future devices that will exceed 15GT/s. As 3-D SiP packaging architectures evolve, advanced codesign tools linked with modeling and simulation capability must be in place to facilitate an effective collaborative environment between system, device and packaging engineers. New materials must be developed to meet the requirements of these new SiP architectures and for meeting (changing) environmental regulatory requirements. As an integrator of components and technologies from different areas, SiP will become the primary architecture for high-value, system-level products for consumer products, before proliferating into products in all major market segments. ■ W.R. (Bill) Bottoms, Ph.D., is chairman and CEO of NanoNexus (nanonexus.com) and chairs the Packaging Technology Working Group (TWG) for the iNEMI Roadmap and the ITRS Roadmap for Assembly and Packaging; wbottoms@nanonexus.com. 48 Circuits Assembly APRIL 2008 circuitsassembly.com http://nanonexus.com http://circuitsassembly.com

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Circuits Assembly - April 2008 Contents Caveat Lector Industry News Market Watch Talking Heads Screen Printing Better Manufacturing Design and Modeling of High-Speed, High-Density 3-D CSPs and Memory Modules The ‘Big Brush Off’ Revisited Impact of Soldering Atmosphere on Solder Joint Formation Beyond Moore’s Law ESD Control For Class 0 ESDS Devices Growing Your Brand This Year’s Model Tech Tips Reflow Soldering Process Doctor Pb-Free Lessons Learned Getting Lean Equipment Advances Apex Product Preview Ad Index Assembly Insider Technical Abstracts

Circuits Assembly - April 2008

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