Circuits Assembly - April 2008 - (Page 62)

ESD Standards This Year’s Model Dr. Charvaka Duvvury and Dr. Harald Gossner Proposed new ESD qualification requirements for HBM and MM. he ESD qualification methods for ICs have a history of requiring performance to human-body-model (HBM) levels of 2kV, and in some cases 200V for machine model (MM). In recent years, CDM has come into focus, but specific requirements are unclear, other than 500V is a good benchmark value. The Industry Council has performed new investigations on ESD Target Levels to establish more realistic levels for HBM and MM. The work was begun following observations that, for the past 10 years, numerous IC product qualifications encountered substantial bottlenecks because of ESD requirements. At the same time, it has become evident no field returns have been attributed purely to ESD damage, even for products shipped at less than the HBM or MM requirements. Simultaneously, rapid advances in silicon technologies, stemming from demand for higher performance circuits, are found to create increasingly restrictive component-level IC pin protection designs incompatible with the IO functions. As a result of these effects, ESD qualifications started involving an exponential cost curve related to silicon respins to achieve the required levels at every advanced tech- T nology node, and eventually circuit degradation at the latest silicon nodes. (This is in addition to factors such as customer delays and extraordinary resources regularly spent by IC suppliers.) To investigate the reality of ESD requirements, the Council launched a thorough investigation with detailed studies by the individual experts. Work was also done to note improvements implemented in ESDprotected areas with basic ESD control methods during the past 10 years. Billions of units shipped during the past five years at lower ESD levels were tracked to study the rate of returns. The following are highlights of this cooperative work: • Basic ESD controls typically practiced at production and assembly areas limit the static voltages generated to less than 500V. • Shipped devices (ICs and discretes) between 500V and 2000V HBM show ESD/EOS related failure rates at <1 DPM after tracking more than 20 billion units with several hundred different designs from different suppliers. • Failure rates of these devices are fully independent of the HBM level shipped. • The same trends are seen for both automotive and non-automotive products. • A vast majority of failure returns referred as ESD/EOS fails are attributed to EOS, and are unrelated to the HBM level. • HBM and MM levels track each other in a design dependent manner. 62 Circuits Assembly APRIL 2008 circuitsassembly.com http://circuitsassembly.com

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Circuits Assembly - April 2008 Contents Caveat Lector Industry News Market Watch Talking Heads Screen Printing Better Manufacturing Design and Modeling of High-Speed, High-Density 3-D CSPs and Memory Modules The ‘Big Brush Off’ Revisited Impact of Soldering Atmosphere on Solder Joint Formation Beyond Moore’s Law ESD Control For Class 0 ESDS Devices Growing Your Brand This Year’s Model Tech Tips Reflow Soldering Process Doctor Pb-Free Lessons Learned Getting Lean Equipment Advances Apex Product Preview Ad Index Assembly Insider Technical Abstracts

Circuits Assembly - April 2008

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