Circuits Assembly - April 2008 - (Page 68)

Pb-Free Lessons Learned Franklin’s Wisdom Why “or equivalent” is the enemy of quality and consistency. bet if I asked 100 assembly process engineers where their bare boards come from, at least 50 would reply “the warehouse.” But how many could actually name the fabricator that’s supplying the warehouse? Probably only the ones who’ve had the lousy luck to experience crushing quality issues. We tend to view PWBs as commodities and don’t afford them special attention – unless they cause a noticeable problem on the production floor. And in this era of ultra-lean staffing, for an issue to qualify as a “noticeable problem,” it is likely pretty sizable. Unfortunately, many fabrication-related issues don’t jump to the top of the defect Pareto. To the contrary, they slowly and stealthily erode yields. They cause a subtle loss of one or two percentage points here and there, and lot-related issues are often transient and temporary. To make matters worse, fab-related defects often get logged under a variety of different modes, which helps to keep their presence buried in the noise and under our radar. There are two things an assembly engineer can do to help fend off fab-related assembly problems: learn their supply chain and review the fab drawings. It’s been my experience the ease with which one can navigate their internal supply chain is inversely proportional to the size of their manufacturing operation. In a smaller organization, where most procurement, production planning and logistics staff work under one roof, it’s easy to get to know who they are and discuss quality concerns. But as the size of the organization grows, so does the degree of difficulty in reaching the right players – some of whom may not be on the same site, the same city, or even the same continent. Despite the potential challenge a larger organization may pose, it is still worth the time to get to know the internal players and suppliers. This is important because if a serious fabrication issue does arise, containment will be much faster and easier, thereby minimizing the financial impact of the problem. Plus, they can help you with fabrication drawing review and changes. Getting the fab drawing and being able to change it also depends on the size of your organization, but, in most cases, it’s worth a shot. The fab drawing contains much critical information for the fabricator about the PWB design and specifications. Some of the information – e.g., layer stackup, minimum feature size and spacing, number of PTHs – is not exceptionally pertinent to the assembler, but other items are. Fab drawings often specify solder mask type and tolerances, final finish, and plating thickness – all of which are extremely important to the assembly engineer. I Chrys Shea is an R&D applications engineering manager at Cookson Electronics (cooksonelectronics. com); chrysshea@ cooksonelectronics. com. Her column appears monthly. The primary purpose of solder mask is to protect traces, which just about all masks on the market can do, but different masks can either help the soldering process or hurt it. Just a few weeks ago I heard about an assembler whose incidence rate of mid-chip solderballs suddenly skyrocketed. The paste, stencils and reflow profiles hadn’t changed, but the type of solder mask had. The new mask didn’t permit errant paste under the component to pull back onto the pad as the previous type had. Because solder mask type can have such a considerable impact on defect generation, mask type should be specified on the fab drawing. When it comes to final finish, disallow any phrases that call for a generic classification, such as organic solderability preservative, and scratch the words “or equivalent” to callouts for any specific products. I encountered this problem many years ago: I was running OSP boards that were soldering horribly, and I called the supplier for help. They asked me if I was actually using their product or a competitive one. (Obviously, I thought I was using their product or I would not have called them for assistance, but that’s not the first time I was wrong and it won’t be the last.) As it turned out, the particular fab shop that made these boards didn’t use the name brand product, and my fab drawing had those nasty little words “or equivalent” after the OSP callout. “Or equivalent” is a subjective term open to interpretation, and in my opinion, it actually contradicts the purpose of stipulating a specific product. Plating thickness has traditionally been part of the boilerplate for fab drawings, but the transition to lead-free soldering presents cause for review. A typical thickness callout for plating that would be subjected to a SnPb soldering process is 18-25 µm, or roughly 0.00075" to 0.001". Concerns with copper erosion and blow-holing have driven many assemblers to increase their spec to 25-40 µm or 0.001" to 0.0015". Thickening the copper layer does not guarantee erosion prevention, but it provides added copper should erosion occur, making the board more robust against extended soldering cycles or rework operations. Benjamin Franklin, the first person on record to intentionally complete an electrical circuit, coined the phrase “an ounce of prevention is worth a pound of cure.” Mr. Franklin was a visionary, but I doubt even he imagined the complex forms and functions that electric circuits would take on 250 years later, or how applicable his piece of seemingly unrelated advice would be. For those assemblers that do not currently have the luxury of prevention, next month we’ll look at some cures – or at least some workarounds – to address common assembly complications that result from board fabrication. ■ circuitsassembly.com 68 Circuits Assembly APRIL 2008 http://www.cooksonelectronics.com http://www.cooksonelectronics.com http://circuitsassembly.com

Table of Contents Feed for the Digital Edition of Circuits Assembly - April 2008

Circuits Assembly - April 2008 Contents Caveat Lector Industry News Market Watch Talking Heads Screen Printing Better Manufacturing Design and Modeling of High-Speed, High-Density 3-D CSPs and Memory Modules The ‘Big Brush Off’ Revisited Impact of Soldering Atmosphere on Solder Joint Formation Beyond Moore’s Law ESD Control For Class 0 ESDS Devices Growing Your Brand This Year’s Model Tech Tips Reflow Soldering Process Doctor Pb-Free Lessons Learned Getting Lean Equipment Advances Apex Product Preview Ad Index Assembly Insider Technical Abstracts

Circuits Assembly - April 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.