Circuits Assembly - June 2008 - (Page 36)

Test and Inspection The Boundary Scan Buzz at Apex New products are leveraging existing technologies – and receiving much broader adoption. hat’s driving interest in boundary scan? What are test vendors doing to address this interest? Introduced in 1990 when the IEEE released the original 1149.1 standard, boundary scan isn’t exactly news. While hardcore boundary scan users are still there, test vendors at Apex in April talked about new interest in boundary scan that is sweeping across big OEMs and EMS companies. Let’s look at motive, means and opportunity behind this surge and gauge what it means for boundary scan going forward. Boundary scan was developed as an in-circuitpowered digital test method primarily to detect solder joint opens and shorts between ICs without the need to physically contact device pins on a board. And, to some degree, boundary scan was also developed to detect faulty ICs through builtin self test (BIST). Boundary scan requires the IC designer to dedicate four or five physical pins, 200 gates of silicon and write boundary scan test code for the IC. In the early 90s, dedicating four physical pins was a big deal for the huge 64 pin DIPS of the day. And, 200 gates were a noticeably significant percentage of the silicon. Fast forward to today, and you might find 100 or more no-connect pins on a BGA, making four TAP pins inconsequential, and 200 gates aren’t even in the noise level on the silicon these days. Boundary scan now can be easily added to the IC with no impact on real estate and little impact on functionality. We have the “means” established, and Moore’s Law tells us this trend will continue. Fault spectrum, fault coverage, limited access, shrinking geometries, higher densities, offshoring, shorter lifecycles, faster speeds – sound familiar? How to effectively test increasingly complex boards and meet today’s production demands is a challenge. Single test strategies are often insufficient, leading to the array of test solutions we see today: ICT, MDA, AOI, AXI, AOXI, benchtop, bare board, on-board, flying probe, vectorless test and boundary scan. The earlier a fault is detected, the cheaper it is to repair. When you can’t probe enough nets to get reasonable fault coverage, or you can’t see enough connections on the board, diagnostic and repair costs start rising and test vendors get creative. The boundary scan standard has thrived since its release and has given rise to three additional specifications, most recently IEEE 1149.6 for highspeed digital circuits, which was ratified in 2003. Circuits Assembly JUNE 2008 W Ted T. Turner is principal at CoGen Marketing Consulting (cogenmarketing.com); ted_turner@cogenmarketing.com. However, today’s innovations in boundary scan are coming not from new standards but from new applications and combinations of existing technologies, as seen on the floor of Apex. The basic standard defines a means to access and control registers within compliant ICs. Today’s boundary scan providers deliver powerful ways to combine boundary scan’s strengths with more traditional test methods: ICT, flying probe and functional. Lowering the overall cost of diagnostics and repair, lowering warranty returns, and raising shipment quality are the “motives” driving a broader view of test solutions, which certainly include boundary scan. “Cellphones are becoming smart phones; TVs are becoming HDTVs; cars have GPS in the dash; computer board communication interfaces are changing and getting faster,” says Peter van den Eijnden of JTAG Technologies (jtag.com). “As well-established test strategies for common products become obsolete, new test strategies are sought.” Disruptive change is opening the door for wider adoption of boundary scan. Boundary scan can structurally test boundary scan devices, non-boundary scan devices and program on-board memory. Disruptive change is the “opportunity” boundary scan has been waiting for. Motive, means and opportunity seem established. Boundary scan is now more widely used for its traditional test coverage, and its applications are being expanded. Goepel’s (goepel.com) VarioTAP touts functional at-speed testing of non-boundary scan parts and comprehensive test coverage for DDR2/DDR3 memory, using integrated microprocessor emulation techniques. Agilent’s (agilent. com) Cover-Extend combines unpowered TestJet technology with powered boundary scan to reduce the number of probes (or increase coverage, when test access is missing) and dramatically increase fault coverage. Apex showcased new boundary scan products and demonstrated much broader adoption. As pressure continues on the cost of test, and technology challenges the ability to test, boundary scan is positioned to play a bigger role. n 36 circuitsassembly.com http://www.jtag.com http://goepel.com http://cogenmarketing.com http://circuitsassembly.com

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Circuits Assembly - June 2008 Contents Letters Caveat Lector Industry News Market Watch Talking Heads Screen Printing Better Manufacturing China Goes ‘Upmarket’ Out of the Garage Improving Production Line Performance Manufacturing Steps Onto the Enterprise IT Stage Measuring and Controlling Wave Height and Dwell Time Wave Soldering Tech Tips Test and Inspection Process Doctor Pb-Free Lessons Learned Getting Lean Eastern Advances Semicon West Product Preview Product Spotlight Ad Index Assembly Insider Technical Abstracts

Circuits Assembly - June 2008

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