Circuits Assembly - July 2008 - (Page 80)

Technical Abstracts In Case You Missed It Cleaning “Methods for Choosing a Saponifier or Surfactant for Printed Circuit Board and Stencil Cleaning Applications” Authors: Ken Wilson, Charles Merz and Aaron Unterborn; ken.wilson@flextronics.com. Abstract: A discussion of technical challenges associated with the selection of chemical additives for PCB and stencil cleaning. Removal of residues from fluxes is increasingly causing problems for assemblers. The heat requirements of Pb-free chemicals have made removing residues difficult, and all residues can cause problems with components that have decreased in size and those with increased electrical sensitivity. The problems associated with residues exist with Pb-free and SnPb organic and rosin-based chemicals. Residues from organic chemicals can cause corrosion or lead to electrochemical migration. Residues from rosin-based no-clean chemicals can cause problems with the application of conformal coatings, test connections, and high-frequency components. High purity deionized water has been unsuccessful in removing many types of residues and can actually contribute to additional problems. For these situations, additional chemical additives, such as saponifiers and surfactants, can be used to assist in removing hard-to-clean residues. These additives are used in all style of cleaners (inline, batch and stencil). Because not all additives have the same formula and can be used with all cleaning processes, manufacturers must decide which additive can be used to clean the residues in question and meet local environmental regulations. The cost of the additive must also must be considered. Because chemical additive use is a large investment for manufacturing facilities, the correct type and concentration must be determined to achieve the appropriate cleanliness level for the least investment. (IPC Apex, April 2008) Packaging Reliability “Line-Spike Induced Failure in Integrated Circuit BondWires” Authors: Dr. S. Kim, K. Choi, M. Peckerar and A. Christou; yskim@physics.umd.edu. Abstract: A novel class of bond wire failure is described to demonstrate that voltage line spikes are of such short duration that they cannot propagate into the chip core circuits to cause internal damage, but rather, the pulse in these spikes is reflected back into the wire itself through ESD circuits and causes power failure. (IEEE International Reliability Physics Symposium, April 2008) Reflow Optimization “A Study of 0201s and Tombstoning in Lead-Free Systems, Phase II Comparison of Final Finishes and Solder Circuits Assembly JULY 2008 Paste Formulations” Authors: Paul Neathway, et al; paul_neathway@jabil. com. Abstract: Tombstoning, the phenomenon where a chip component stands on one end during reflow, is well documented and understood in SnPb systems. It is reported to occur more frequently in Pb-free systems, and smaller components are at greater risk than larger ones. A comprehensive DoE was undertaken to characterize tombstoning of 0201 components in different metallurgical solder systems. Factors included pad geometry, board finish, stencil geometry, solder paste type, print and placement offsets, and reflow profile and atmosphere. The experiment was divided into two phases; the results of Phase II are analyzed and reviewed. (IPC Apex, April 2008) “The Graping Phenomenon: Improving Pb-Free Solder Coalescence through Process and Material Optimization” Author: Tim Jensen; tjensen@indium.com. Abstract: As small surface-mount components such as 0201 and 01005 packages have entered volume assembly, manufacturers are observing increased instances of poor solder coalescence during reflow. The root cause is the change in oxidation behavior at very low volumes of deposited paste. A solution is required, both to restore a high-quality appearance to solder joints and to maintain customer confidence. Comprehensive analysis of factors, including material selection, print process settings, reflow profile, and factory-floor practices highlights a number of measures that solve this issue cost-effectively and without impairing reflow of other components on the board. (IPC Apex, April 2008) Tin Whiskers “Effects of Tin Mitigation Processes on Whisker Growth and Solder Joint Reliability for Chip and Small-Outline Package Components” Authors: Tom Lesniewski and Tom Higley Abstract: This paper reports the results of an evaluation of tin mitigation processes for components; i.e., converting parts with pure tin and other Pb-free finishes to SnPb finishes. In this study, three groups of components were evaluated: pure tin piece-parts (control group), pure tin parts installed on PCBs with Sn63, and pure tin parts mitigated with Sn63 solder installed on PCBs with Sn63. The primary objectives of the testing and analyses were to determine if 1) tin mitigation processes introduced mechanical damage or degradation to the parts, 2) tin mitigation processes were effective in reducing or preventing tin whisker growth, and 3) quality and reliability of the solder joints were affected by tin mitigation processes. (IPC Apex, April 2008) circuitsassembly.com CirCuits Assembly provides abstracts of papers from recent industry conferences and company white papers. With the amount of information increasing, our goal is to provide an added opportunity for readers to keep abreast of technology and business trends. 80 http://circuitsassembly.com

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Circuits Assembly - July 2008 Contents Caveat Lector Industry News Market Watch Talking Heads Focus on Business Global Sourcing On the Forefront Screen Printing Tech Tips Will Electronics Follow the Sun? ‘Warm’ Manufacturing Heats Up Reputation Trumps Recession, China ‘Web Circuits’ A Novel Non-VOC Conformal Coating Krypton: Benchmarking Customer Satisfaction 2008-09 CIRCUITS ASSEMBLY Buyers Guide Wave Soldering Pb-Free Lessons Learned Process Doctor Materials World SMTA Int'l Product Preview Ad Index Assembly Insider Technical Abstracts

Circuits Assembly - July 2008

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