Printed Circuit Design & Fab - June 2008 - (Page 24)

DFA / dFt FiGurE 3. This is the typical land pattern as defined by the CAD system. The center of pin 1 is used as the index for the component. Here, a grey marker indicates the true center and rotational orientation required for the component. FiGurE 4. Here is the actual stencil representation for the pads represented in Figure 3. common platform for all results to be collected and reported. This common neutral data format also ensures that all reviewers are analyzing the same product design data, which leads to a consistent analysis of the data across the various reviewers. Typically, specific groups will be responsible for performing the different types of analysis listed above, as they are considered the domain experts in these areas. However, the results of their individual analysis need to be aggregated and shared across the enterprise to derive a complete set of results that is fed back to the design team for consideration. A further benefit of a common data format is easy adoption of low cost, easy to use viewing tools. Easy access to the information under review increases the number of groups and people who can participate in the review process, yielding better results sooner. During the review process, reviewers check the design to ensure it conforms to the design guidelines. In an automated environment these guidelines translate into Design Rule Checks (DRCs). During the analysis process, if a design rule violates the guidelines, the violation is indicated in the data with a DRC marker. DRC markers form an intelligent way to indicate a violation of a design rule; they can be used to highlight issues in the layout that need to be addressed or changed in the design prior to beginning manufacture. DRCs can also be used for tracking purposes during the review, or as a means of showing a problem back in the authoring tool. For example, a DRC marker may show where two traces are spaced too closely. They may also indicate missing or an insufficient number of fiducials used for alignment purposes during the manufacturing process. In FiGurE 1, a DRC marker is indicating a DfA issue where two components have been placed too close to each other. This may cause defects during the assembly process, due to manufacturing variation in the placement of these two components. In more advanced scenarios, these DRC markers may also contain comments that were made by individual reviewers, possibly captured over multiple review cycles. When all analysis and review is completed, the information is communicated back to the designer for disposition. The designer now has accurate, unambiguous feedback to decide what corrective actions need to take place to improve the product design for manufacturing. 24 Design for Test When performing DfT analysis, understanding the actual electrical test access points is critical. The external copper layers, solder mask layers, component outlines and net lists must all be available to accurately determine the actual electrical accessibility of the design, and correspondingly, to calculate the actual test coverage. The old rule-of-thumb of one test point per net is insufficient for the majority of today’s PCBs. If the board has some form of powered up test, additional test points that are separate from the measurement test points are required to apply this power to the board. If boundary scan is available on the board, certain nets may not even need a test point, as there may be enough test capability using the boundary scan cell. In this scenario, the net should indicate that it does not need a test point, and the DfT analysis adjusted automatically. Resistors, capacitors, and inductors may need additional test points on either side of the components for four-wire measurements that increase accuracy on certain types of value. Once the test probe and corresponding alternate accessible locations have been finalized, they need to be communicated to manufacturing. This information becomes increasingly important for debugging test programs as well as repair. On large boards with incomplete silk screens, being able to quickly enter probe names listed on fault tickets and relate them to the corresponding nets can significantly decrease the mean-time-to-repair issue. FiGurE 2 shows the result of the DfT analysis on an example board. The component outline in green is used as a keepout area for test probes. The white regions are exposed metal that are analyzed for valid test probe locations. If enough test regions are available for sufficient coverage, test probes can be placed, such as the yellow probe labeled 186. Transitioning Design Data into Manufacturing The physical design data is just one part of the information required to manufacture a printed circuit board. Another critical item is the production BOM data. As opposed to the design BOM, the production BOM represents exactly which version of a PCB design will be manufactured. The production BOM also typically comes from a separate business system within the company, not the design data. BOMs are JUNE 2008 printEd circuit dESign & fAB

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Printed Circuit Design & Fab - June 2008

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