Printed Circuit Design & Fab - June 2008 - (Page 28)

SIGNAL intEGrity inductance seen at the microstrip line. Depending on the number of grounded pins and their locations, different inductance values are obtained. FiGurE 6 shows four possible configurations and the corre! FiGurE 6. Inductance values detersponding inductance mined by PowerPeeC for different values as determined ground pin configurations. by PowerPEEC. The horizontal spacing of the pins is 2 mm and vertical spacing is 1.4 mm. Note that the white pins are considered as floating for the purpose of inductance computation. The values of inductance show !FiGurE 7. Inductance experienced by strong dependence two pins of the same differential pair on the ground pin may be different. configuration, ranging between 16 nH to 37 nH for all the experiments performed on this connector. FiGurE 7 illustrates another important point; that the loop inductance seen at two pins of a differential pair may vary depending on their locations. For the AIRMAX connector used in the measurements, the loop inductance for pin 1 is 26.6 nH whereas pin 2 shows 23.6 nH. Similarly, pins 3 and 4 have loop inductances of 31.8 nH and 28.8 nH, respectively. This will cause propagation delay mismatch between the two leads of a differential pair, creating more skew in the connector. Although the results obtained by PEEC simulation will be highly accurate, depending on the number of pins, the model size and corresponding simulation time could be large. For example, for the AIRMAX connector, the number of pins could be as high as 120, and the PEEC simulation could take tens of minutes for a single ground pin configuration, making for a time consuming search for the optimal configuration. Therefore, a faster method of exploring different connectors and ground configurations that also yields reasonable accuracy should be used. Magnetic energy Conservation Method. For measuring the loop inductance caused by a connector, the method described by Krauter and Mehrotra is found to be appropriate and convenient. The method determines the equivalent loop inductance based upon the conservation of magnetic energy stored in the conductor system. For the AIRMAX connector, each pin has two segments of unequal length – one horizontal and one vertical. For the purpose of inductance computation, a unit current source is applied between the horizontal terminal of the signal pin and the terminal, 28 shorting all horizontal terminals of the ground pins. The terminals of the vertical portion of all pins will be considered shorted assuming quasi-static mode. For applying the energy-equivalence method to a system consisting of a signal line and N ground lines, let the signal line be represented by the subscript s and the ground lines using gi where i is the index of the ground line. The quantities corresponding to the horizontal (vertical) conductors will be denoted by superscript H (V). Let I be the vector of currents flowing through each pin (with directions signified by the sign of the current value) for unit current through the signal pin. The partial inductance matrices for the horizontal conductors, MH, and the vertical conductors, MV, will be given by the following matrix considering the respective parts only: Ls M g 1s M sg1 L g1 M g 2 g1 M g1g 2 M sgN Eq. 1 MP which is the total magnetic energy stored for unit signal pin I MH 0 Equation I Lloop 1 I ( M H M V )I T current, then I 0 MV I I MH 0 Lloop I I I ( M H M V )I T Eq. 2 Equation 2 0 MV I M sg1 M sgN H Ls M gNs L M g 1s L g1 M g1g 2 gN MP The L terms M g 2 g1 represent the partial self inductances and the Equation 1 M partial If the equivalent loop inductance is Lloop, LH M terms the gNs gN This formulation produces a huge speedup in inductance Equation 2 computation – more than four orders of magnitude – with inductance values within 5% of the values obtained from PowerPEEC, as shown in taBlE i. Therefore, this formulation can be utilized for determining the optimal ground pin configuration, quick inductance computation for signal integrity analysis and many other applications. Effects on Eye Diagram The DUT that produced Figure 2 through Figure 5 is modeled for signal integrity analysis to account for the common mode noise, which is typically ignored in conventional signal integrity simulations. For our simulations, the ground-toground noise is injected as a sine wave for simplicity, with peak-to-peak voltage equal to the peak-to-peak ground noise. FiGurE 8 shows the simulated eye diagram, which mimics the parBERT measurement in Figure 2, using 128 random bits simulated in a repeated fashion for 150 ns at taBlE 1. PeeC versus Fast Method Modeling. powerpeec (nh) 37.17 27.99 18.84 25.22 16.85 20.97 18.23 16.53 Fast Method (nh) 38.43 29.27 18.41 25.23 16.55 20.69 18.37 16.99 percentage error 3.37 4.59 -2.28 0.07 -1.85 -1.38 0.77 2.70 JUNE 2008 printEd circuit dESign & fAB

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Printed Circuit Design & Fab - June 2008

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