Printed Circuit Design & Fab - July 2008 - (Page 16)

The Z-Direction Goes vertical Electronics companies across markets are hopping on PoP. WHen lAnD IS lIMITeD, builders construct high-rise condos and apartments. When board real estate is limited, packages also go in the z-direction. Some of the high growth areas include stacked die CSPs and package-on-package (PoP). Next in the progression of technologies moving in three dimensions is through silicon via technolE. jAn ogy for stacking silicon devices. vArdAmAn Stacked die CSPs. Driven by portable applications that require extremely small form factors, shipments of stacked die packages have grown dramatically in the past five years. Stacked die inside CSPs are found in mobile phones and a variety of consumer products such as cameras and camcorders. More than 2.5 billion packages were shipped in 2007, and the number is expected to grow in 2008.1 While the first applications had two stacked die, the average number of die in a stack is increasing. Shipments of stacks with four or more die are common, and some companies have moved into production with stacks of six to nine die – some containing both logic and memory. Hynix has demonstrated a 20-chip memory stack in an R&D project. Typical die thicknesses in production range from 75 to 125 µm for conventional die stacking. Stacked die are still largely wire bonded, but flip chip use is beginning to increase. Package-on-package. According to Amkor, PoP is one of the company’s fastest-growing packages, and may be one of the industry’s, too. With almost 150 million top and 150 million bottom packages shipped last year, and an installed base of more than 150 mounting systems from a variety of companies, Amkor is probably right. Today’s applications include mobile phones (the largest), digital cameras, and MP3 players. Future applications include medical products, laptops and ultra-mobile PCs. Amkor has developed a through mold via technology for next-generation PoP. It will scale with trends in the top memory package as pin counts increase, pitch transitions below 0.5 mm, and the solder balls move beyond two rows to multi rows. The new process follows a standard mold array process flow, but uses a laser to open vias (FiGurE 1). Stacking die inside the package results in the thinnest package with the highest board-level reliability and lowest assembly cost compared to other z-direction packages. This package however, is not always the best choice when a logic device is added. PoP was developed because it offers several advantages over stacked die packages, especially where there is a need to stack logic and memory. Each package can be individually tested before stacking. Two packages from different suppliers can be stacked and it is easy to change memory capacity. The cost of a known good memory die may be almost the same as a packaged 16 die. This can decrease the margin of the stacked die supplier. If known good die are not used, yield issues are compounded. There are some disadvantages to PoP. Package cost may be higher for the PoP configuration than for stacked die CSP because there are two substrates rather than one. Co-planarity of the two packages, especially during reflow, was an issue in the early days, but a tremendous amount of work has been done to alleviate this problem. Substrate warpage has been the key issue, and a number of companies have developed solutions. Both the top and bottom packages must be optimized. The liquidus/reflow temperature is the most critical in the process. Amkor has conducted extensive package warpage optimization studies varying both substrate thickness and mold materials. Substrate design rules (routing), core thickness, copper ratio and prepreg materials have been optimized. Die thickness and material properties also had to be optimized, while mold compound filler size, CTE, Tg, shrinkage and thickness had to be carefully specified. Amkor found that a very flat top package is key to good stacking yields. Several companies, including Henkel and Indium, have introduced flux materials. Henkel’s epoxy flux, for instance, shows good connectivity and increased reinforcement.2 While there have been concerns over package height, which is thicker than the traditional stacked die package, solutions are being developed. These include embedding devices in the substrate, thinner substrates and concepts such as Tessera’s MicroPILR package. The top package typically contains high capacity or combo memory devices. The bottom package typically contains a high-density logic device. Body sizes range from 10 x 10 FiGurE 1. Size advantages using through mold via technology for memory interface density scaling in next-generation PoP . Higher performance memory architectures and smartphone size reduction requirements require bottom PoP technology that can scale in density with CSP ball/pitch density trends. JULY 2008 printEd circuit dESign & fAB

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Printed Circuit Design & Fab - July 2008

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