Printed Circuit Design & Fab - July 2008 - (Page 18) electrodeposition of Copper, Part 2 Advanced technology PCBs require electrolytic copper capable of excellent throwing power and leveling. WITH SMAller DIAMeTer vias and thicker panels, the importance of a high throwing power, high leveling acid copper electrodeposition process takes on added significance. In order for high aspect ratio vias to withstand multiple thermal cycles, the copper plating within the via micHAEl must be uniform and have optimum cArAno physical properties. Additionally, the quality of the copper deposit depends in part on the performance of the initial metallization process that has been previously discussed. er aspect ratio through holes. For example, the ohmic resistance (or voltage drop) can be explained by the following model: E= JL2 2Kd Eq. 1 Mathematical Modeling of Plating Uniformity There are a number of published studies on the subject of plating uniformity in through holes. In these studies, researchers developed models to test plating uniformity. With respect to plated through holes, the models attempted to predict what influence key variables had on plating uniformity. The variables include: ■ Mass Transport ■ Ohmic resistance ■ Electrode reactions ■ Circuitry layout Basically, one has to optimize the electrolytic copper process for plating on the surface and in the through hole. Studies indicated that ohmic resistance tended to dominate the plating process with the high- ! FiGurE 1. The fishbone diagram outlines the interactions that occur during the electrolytic copper plating process. 18 Where E is the ohmic resistance, J is cathode current density, K is solution resistance, d is hole diameter and L is length of hole (board thickness). As the model shows, the thickness of the panel or length of the hole influences the difficulty of plating by a squared term. In addition, an optimal balance between agitation on the PCB surface and solution movement in the holes was required to achieve a compromise between uniform plating distribution across the panel surface and excellent throwing power in the hole. The model developed by these scientists has been verified time and time again. Plating uniformity is a continual challenge for through-hole PCB manufacturing and is becoming more difficult with increasingly complex designs. It should be quite clear that plating uniformity is closely influenced by solution chemistry and solution agitation conditions. Certainly, understanding the ramifications of the model is critical with respect to plating distribution, throwing power and overall plated through-hole reliability. The factors listed in the fishbone diagram below provide a framework for discussion. These and other variables will be discussed in this and subsequent columns. The fishbone diagram in FiGurE 1 highlight the numerous interactions that occur during the electrolytic copper plating process. The function of the basic chemical components in an electrolytic copper bath are listed below: Copper Sulfate. Provides source of copper (+2) ions. Sulfuric Acid. Provides solution conductivity and anode corrosion. Chloride Ion. Plays a synergistic role with organic additives in the brightening and leveling mechanism. Also promotes even anode corrosion. organic Addition Agents. There are a myriad of addition agents commercially available. The function of these additives is to provide a mechanism whereby the copper deposit is plated in a level and ductile condition. Typically, the addition agent package consists of grain refiners, leveling agents and suppressors. For purposes of this discussion, the grain refiner is used interchangeably with the term “brightener.” JULY 2008 printEd circuit dESign & fAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - July 2008 Printed Circuit Design & Fab - July 2008 Printed Circuit Design & Fab - July 2008 - (Page Cover1) Printed Circuit Design & Fab - July 2008 - (Page Cover2) Printed Circuit Design & Fab - July 2008 - (Page 1) Printed Circuit Design & Fab - July 2008 - (Page 2) Printed Circuit Design & Fab - July 2008 - (Page 3) Printed Circuit Design & Fab - July 2008 - (Page 4) Printed Circuit Design & Fab - July 2008 - (Page 5) Printed Circuit Design & Fab - July 2008 - (Page 6) Printed Circuit Design & Fab - July 2008 - (Page 7) Printed Circuit Design & Fab - July 2008 - (Page 8) Printed Circuit Design & Fab - July 2008 - (Page 9) Printed Circuit Design & Fab - July 2008 - (Page 10) Printed Circuit Design & Fab - July 2008 - (Page 11) Printed Circuit Design & Fab - July 2008 - (Page 12) Printed Circuit Design & Fab - July 2008 - (Page 13) Printed Circuit Design & Fab - July 2008 - (Page 14) Printed Circuit Design & Fab - July 2008 - (Page 15) Printed Circuit Design & Fab - July 2008 - (Page 16) Printed Circuit Design & Fab - July 2008 - (Page W1) Printed Circuit Design & Fab - July 2008 - (Page W2) Printed Circuit Design & Fab - July 2008 - (Page W3) Printed Circuit Design & Fab - July 2008 - (Page W4) Printed Circuit Design & Fab - July 2008 - (Page W5) Printed Circuit Design & Fab - July 2008 - (Page W6) Printed Circuit Design & Fab - July 2008 - (Page W7) Printed Circuit Design & Fab - July 2008 - (Page W8) Printed Circuit Design & Fab - July 2008 - (Page W9) Printed Circuit Design & Fab - July 2008 - (Page W10) Printed Circuit Design & Fab - July 2008 - (Page W11) Printed Circuit Design & Fab - July 2008 - (Page W12) Printed Circuit Design & Fab - July 2008 - (Page W13) Printed Circuit Design & Fab - July 2008 - (Page W14) Printed Circuit Design & Fab - July 2008 - (Page W15) Printed Circuit Design & Fab - July 2008 - (Page W16) Printed Circuit Design & Fab - July 2008 - (Page 17) Printed Circuit Design & Fab - July 2008 - (Page 18) Printed Circuit Design & Fab - July 2008 - (Page 19) Printed Circuit Design & Fab - July 2008 - (Page 20) Printed Circuit Design & Fab - July 2008 - (Page 21) Printed Circuit Design & Fab - July 2008 - (Page 22) Printed Circuit Design & Fab - July 2008 - (Page 23) Printed Circuit Design & Fab - July 2008 - (Page 24) Printed Circuit Design & Fab - July 2008 - (Page 25) Printed Circuit Design & Fab - July 2008 - (Page 26) Printed Circuit Design & Fab - July 2008 - (Page 27) Printed Circuit Design & Fab - July 2008 - (Page 28) Printed Circuit Design & Fab - July 2008 - (Page 29) Printed Circuit Design & Fab - July 2008 - (Page 30) Printed Circuit Design & Fab - July 2008 - (Page 31) Printed Circuit Design & Fab - July 2008 - (Page 32) Printed Circuit Design & Fab - July 2008 - (Page 33) Printed Circuit Design & Fab - July 2008 - (Page 34) Printed Circuit Design & Fab - July 2008 - (Page 35) Printed Circuit Design & Fab - July 2008 - (Page 36) Printed Circuit Design & Fab - July 2008 - (Page 37) Printed Circuit Design & Fab - July 2008 - (Page 38) Printed Circuit Design & Fab - July 2008 - (Page 39) Printed Circuit Design & Fab - July 2008 - (Page 40) Printed Circuit Design & Fab - July 2008 - (Page 41) Printed Circuit Design & Fab - July 2008 - (Page 42) Printed Circuit Design & Fab - July 2008 - (Page 43) Printed Circuit Design & Fab - July 2008 - (Page 44) Printed Circuit Design & Fab - July 2008 - (Page 45) Printed Circuit Design & Fab - July 2008 - (Page 46) Printed Circuit Design & Fab - July 2008 - (Page 47) Printed Circuit Design & Fab - July 2008 - (Page 48) Printed Circuit Design & Fab - July 2008 - (Page Cover3) Printed Circuit Design & Fab - July 2008 - (Page Cover4)
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