Printed Circuit Design & Fab - July 2008 - (Page 28)

CO-dESiGn innovative modeling supports Co-desigN of the PoWer sUPPlY ChAiN, Part 1 New software tools ease problems associated with power delivery design in large computer systems. by DaviD Quint and CHarles Keen Since that time, there has been the In the late 1990s, the Hewlett-Packard opportunity to redesign several CPU Company entered the marketplace with and ASIC packages and learn a great a large server under the name “Superdeal in the process. These techniques dome.” This event actually represented include a suite of simulations that evala new dimension in the integrated uate the performance of the integrated circuit and package design area. The system from several viewpoints, includvoltage/current pinch and clocking freing methods of interfacing between the quencies of the IC’s contained in this IC, the package, and the printed circuit new system had increased so dramatiboard, either using a fully detailed cally that designers had to design a new package model, or with a simplified tool to model and simulate the power (IBIS-like) model. The use of simplidelivery system (PDS) with a higher fied models for assemblies, including level of detail. the packaged IC, can be a time saver, A voltage/current “pinch” had especially if the simplified model is occured when designers used lower used multiple times at the next level of voltages and higher currents at the simulation. integrated circuit level in order to pack more gates in the same amount of silicon area without increasing power density. This new generation of IC technology allowed increased complexity while maintaining power per unit area. However, it also created this “pinch” for power delivery, since current increases drawn by the IC, are inverse to the supply voltage, and create larger I*R and L*dI/dt drops in the package, the PCB, and the converter. The “pinch” was tightened by smaller voltage tolerances scaled to the lower supply voltages. Higher currents stress ! FiGurE 1. Graphical depiction of the package power planes, solder joints, SPICe model of a package, two layers and PCB power planes, causing excessuperimposed, to illustrate the level of sive heating and reliability problems. detail of the model. 28 The original tool was actually a large scale SPICE model built in three dimensions. Planar constructions such as IC packages and printed circuit boards can be represented by a stack of two-dimensional square grids, representing the conducting planes, connected vertically with simple circuits representing vias or groups of vias, as shown in FiGurE 1. Planes and vias are represented as sub circuits including inductances, inter-plane capacitance and resistors as lossy components. Components such as capacitors and resistors are represented with sub circuits, including parasitics of the components and connecting vias. The IC can be represented by a grid of time varying resistors, bypass capacitors, and parasitics, rather like a multi-port IBIS model. The graphical depiction used by the tool is not a conventional schematic, but a map of lines and circles with labels. The model is assembled with the use of a script, which leaves a two-and-onehalf dimensional depiction that can be edited manually. The final graphical model shown in FiGurE 2 is then processed into a threedimensional SPICE deck, which is a massive interconnection of sub circuits. The components of the sub circuits must then be evaluated by the user, which is JULY 2008 printEd circuit dESign & fAB

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Printed Circuit Design & Fab - July 2008

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