Printed Circuit Design & Fab - July 2008 - (Page 29)

Until recently, the SPICE model approach to package and board analysis was running out of steam because run times were getting too long. In the course of trying to speed up SPICE simulations, we tried comparing different vendors’ SPICE products using the same circuit. We determined that the compute time for at least one new SPICE engine was dramatically improved. For example, we found that a 25,000 node SPICE model could be run in about 20 minutes using a newer SPICE solver where it had taken more than eight days previously. This decrease in processing time is a significant productivity factor. Power Delivery System Evaluations ! FiGurE 2. Above figure zoomed in to show the individual bars, circles, and notes that identify the sub-circuits, each of which contains one r, one l, and one C. not as daunting a task as it may seem. This SPICE circuit can then be evaluated, yielding voltages, currents, powers, etc. at almost any location within the package. The model is ready for SPICE evaluation in any mode: DC, AC, and Transient simulations can all be done on the same model with minor modifications. Since the graphical interface does not depend on extraction from a layout tool, it is easily modified for speculative changes and can be used at an early stage in the system design process. On the other hand, most power analysis tools do their models from an extraction of design layout information of an EDA tool. This appears to be a convenience for the power designer, but it delays critical design decisions until late in the design process. We have found that, even though the accuracy of the layout may be less than ideal, the ability to evaluate the performance at an early stage is highly desirable. A common problem with all PDS analysis tools appears to be the complexity of doing the analysis itself. The device being modeled must be divided into a large number of sub-sections in order to accurately capture the geometric effects of small features. For example, we have found that CPU run times of a week or more can easily happen where a large package is concerned. Where long run time is necessary with a system model, computation time can be speeded up considerably by partitioning the model and substituting simplified units for certain sections of the system model. The simplified model can also enhance communication between levels of the system where the IC design, package design, and system board design are done by different groups. The final section of this paper seeks to explain some of these techniques. JULY 2008 The first simulations with the three-dimensional models yielded much more information, and more accurately, than we had ever created before. Much of this accuracy came from the use of a distributed model. With that information in hand, engineers quickly embraced the process, using the new data mainly to improve design accuracy and reduce project risks. Prior to this, the power delivery modeling consisted of a manually calculated one-dimensional network, with consequent errors that often required late corrections based on measurements. A new process for evaluation of the PDS evolved to include six distinct categories of performance metrics. The important point is that not all of the information produced by the new analysis is useful, so there must be a system for evaluating the data. Some of these categories are more important than others, and my purpose is to explain the importance of each one. Briefly, the six categories are: DC voltage Drop. This can be done with a uniform current or detailed map of currents across the die. Actual currents in full activity are used here. The results can determine if excessive voltage drops occur at specific locations on the die. In addition, currents measured at the C4 or bump locations can reveal current density issues or locations exceeding current specifications. In the PC board context, excessive voltage drops and localized heating of planes and vias are printEd circuit dESign & fAB 29 http://www.pcbpool.com http://www.pcbpool.com

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Printed Circuit Design & Fab - July 2008

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