Printed Circuit Design & Fab - July 2008 - (Page 30)

CO-dESiGn !FiGurE 4. Current map of the board PDS plane underneath the ASIC. The current magnitudes in the actual plot are color coded. Plots of this type can highlight current pinches and hot spots. !FiGurE 3. voltage map in a 1.2v power plane with a large ASIC near center. vrM source is toward the bottom. voltage contours can be seen in gray scale, where the original is in color. Plots of this type can highlight hot spots and/or suggest layout improvements to improve performance. important issues. The information can also be used to locate sense points for voltage regulation. AC Impedance looking into the PDS. From the IC perspective, the package PDS has an equivalent impedance vs. frequency. IC parasitics and bypass need to be included to simulate the response of the merged system. The IC model is a grid of current sources, which add up to 1 amp, all phases at zero. These sweeps can be useful primarily to observe those components or features causing PDS resonances. Beyond that, the model can be used to optimize the frequency response of the PDS by damping out or moving resonances to provide a flatter Z(f). This is easily done by trial and error, by changing bypass cap values and locations. The results of this action can be seen graphically in the transient simulations shown. The die circuit will usually be divided into several blocks, with different current loads, so the single impedance value may not be precise enough for a large IC, and the distributed model would be required. In addition, there may be several power domains that would need to be evaluated individually. Transient Step Current. This test requires some knowledge of the steady-state operating points of the IC, including leakage and active currents. Generally, the die will be at a low current state if it is idle from a processing standpoint, and jump to a high current draw when called up to full activity. This will produce a “dip” in voltage followed by an overshoot and ringing. This is the most fundamental characteristic of the IC current, and it can reveal problems with inadequate die, package bypassing or PDS resonances. Determining the level of activity or the rise time of the current steps on other vendor’s parts can be difficult to obtain. Killer virus Time Domain Simulation. This is an extension of the transient step current simulation. It is possible, 30 though not likely, that the operation of the die could be directed to cycle from high to low and back at a frequency corresponding to a resonance of the PDS. In this case, the die cyclical voltage could increase in amplitude over several cycles and kill the operation of the die. In simulation testing, this is still considered to be the worst possible stress of the PDS. Transient Active Current. Once the die design has progressed enough to determine the high frequency switching current drawn by the circuit blocks, these currents can be simulated in the PDS model. The IBIS-like load models are driven separately, or in blocks to fill the grid of die connections. This could also be done in AC mode, but IC designers generally find the time domain graphs more useful. For example, transient current events on the die can occur at the clock frequency, which is usually many hundreds of megahertz and may cause the supply voltage to drop below spec. These transients are usually well above the useful frequency range of the package bypass design. Faced with this, the IC designers can take actions to move timing events to reduce current spikes, or increase die bypass capacitance. Also, this simulation yields a great deal of information at the package/ PC board interface which can be used to generate specifications and/or simplified models for PC board designers. leakage of High Frequency noise. When generated at the die level into the PC board power domain, this is a difficult problem to simulate. This could contribute to EMI problems and/or create power related interactions that could limit performance, especially where a large number of IC’s are used in close proximity. Usually, the same model for the package can be used, but the simulation needs to be modified slightly to measure the effects in question. DC Voltage Drop This is the most fundamental criterion for the operation of the circuitry on a system board. As simple as it may seem, it should not be taken lightly. The problem can be as simple or as complex as the package or board layout. The voltage/ current pinch can happen at any point in the system, and JULY 2008 printEd circuit dESign & fAB

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Printed Circuit Design & Fab - July 2008

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