Printed Circuit Design & Fab - July 2008 - (Page 31)

CO-dESiGn ent levels of the PDS, while at the same time simplifying and if the designer does not have a good two- or three-dimenexpediting the task. pcd&f sional simulation capability, significant errors or omissions can be hidden from view. Voltages in the printed circuit board can usually be probed to find excessive drops. This Ed. note: This work was previously presented at DesignCon information is particularly useful in determining the proper 2008 and is published in Printed Circuit Design and Fab with copper thickness to use for the power and ground planes, or the permission of the authors. if additional planes are needed in the board stack up. Currents can be measured in planes and vias to look for places where overheating may occur. This can be a serious problem, particularly under parts with very small pitch and high dr. davE Quint is a master engineer at HP working on current densities. In the past, most boards were designed IC fabrication, package design, signal integrity, and power without 2-D simulations However, the changing industry is delivery system integrity and can be reached at dave.quint@ putting a “pinch” on costs and time to market as well, so hp.com. charlES kEEn is an analog engineer for HP and the lab that has the better tool set for board design will have can be reached at charles.keen@hp.com. the advantage of fewer board turnarounds. Errors in the package are much harder to fix, since prototype turnaround times are much longer for packages, and costs are highBringing a world er. The package designer must have accurate of information to you knowledge of the DC current drawn by the IC, including the distribution map for a larger die. A three-dimensional model of the package power circuit may be essential to finding overheated bonds or vias and localized voltage drops as well as heating of the planes of the package. FiGurE 3 illustrates a plot of supply voltages on a certain power plane within a PC board. The actual plot is in color, which allows voltage drop are subject to be more easily seen. There are no problems in this design, but it illustrates that the current distribution and voltage drop is subject to the shapes of the planes, the placement of sources and loads, and even upon the presence of via keep-outs and thermal relief patterns, which all increase the effective resistance of the planes. Currents can also be displayed as in FiGurE 4, and hot spots and current pinch areas can usually be found. Computer dis“I’m glad I attended IPC Midwest to learn about solutions to challenges plays will take advantage of colors to display we are seeing, especially with lead free. It’s important to have a forum magnitudes. like this where critical industry issues can be discussed.” There are a number of problems associRobert Cook, Technical Fellow, ated with delivering power reliably within a Visteon Corporation, Van Buren Township, Michigan large computer system. Many smaller system manufacturers have not had to deal with these Keep up with global changes in technology, standards and customer expectations. issues on a large scale, but advances in the If you need to see electronics assembly or PCB equipment, technology are likely to make these problems you need to be at this show! much more commonplace. While there are many new software tools designed to deal PRINTED BOARDS ELECTRONICS ASSEMBLY TEST with these technical hurdles, there is still some confusion surrounding how they are to Sunday–Thursday, September 24–25, 2008 be used, and how to correlate simulation data Renaissance Schaumburg Hotel & Convention Center through the system hierarchy. In Part 2 of this Schaumburg, Ill article, we will propose an approach, includwww.IPCMidwestShow.org ing basic, essential, and advanced methods of measuring performance of the PDS, explore methods for linking the simulations of differJULY 2008 GET INTERCONNECTED printEd circuit dESign & fAB 31 http://www.IPCMidwestShow.org http://www.IPCMidwestShow.org

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