Printed Circuit Design & Fab - July 2008 - (Page W11)

PR O FESSI ON AL D EVE L OPME NT CE RTIF ICATE PROGRA M whether new to the profession or experienced veterans of 30+ years. The reality is that there is seldom one perfect way to place parts on a PCB. However, out of the hundreds or thousands of possible variations, there usually are only a few that make sense. Understanding how to determine what those few are is the secret to placement. Once parts are placed, there are hundreds of possibilities for routing the many transmission lines of the circuit. Like placement, only a few variations really work well. Determining which placement and routing schemes optimize the design is a matter of physics, ﬁt and opinion. This full-day tutorial will focus on both the science behind placement and routing, and the opinions of the instructor. This course will cover placement for optimum routing, placement “Rooms” (several views), and placement’s effects on the schematic, EMI, board stackup, fabrication, testability, repair and assembly. It will also cover a typical design ﬂow, routing plans, routing for best signal integrity, what’s most important when routing, signals of greatest concern, I/O structures, differential pairs, analog vs. digital, and much more. In today’s high-frequency designs, clock speeds of 1 GHz and edge rates less than 1 nsec are common. These high frequencies and their harmonics must be bypassed properly between power and ground to ensure power delivery, switching ﬁdelity and control of radiated emissions. To ensure that the power delivery system meets its objectives, the intelligent placement, value, size and type of capacitors must be achieved. Also, at higher frequencies, the die and interplane capacitance must be optimized. Proper via placement for return current pathway minimization, laying out digital/analog interfaces, pours (Cu ﬁlles) and splits must be carefully analyzed. This full-day tutorial will illustrate a layout process that achieves 0.1 Ohm up to the knee frequency and provides methods to minimize serial/parallel resonance and achieve constant ESR. new technologies. However, much of the blame may be attributed to a lack of understanding the manufacturability rules associated with these technologies. As a designer, we should be designing for the most cost-effective product without sacriﬁcing performance. Cost reduction, by design, forms the fundamental building blocks for this session. This full-day tutorial will be divided between lectures and interactive discussion groups. The discussion groups will explore, under guidance, material issues for lead and lead-free environments, high performance, HDI, assembly and surface ﬁnishes for various environments. The tutorial also will look at the impact of demands placed on our industry by a growing number of lead-free directives on fabrication and assembly processes. Finally, the groups will discuss new and innovative ways to test and verify a product’s integrity in both current and lead-free products. There will be ample time allocated to look at individual challenges faced by attendees. Each attendee should gain a clear understanding of overall DFM issues and how they relate to current technologies, as well as lead-free directives. 9 am – 5 pm T5 – Basics of DFM Speaker: Gary Ferrari, FTG Circuits Lead-free, small-pitch BGAs, microvias, embedded passives, controlled impedance, EMI, what next? Each of these technologies presents manufacturing challenges that must be addressed by both today’s designer, as well as any cost-reduction team. We ﬁnd it easy to blame escalating costs on these 9 am – 5 pm T4 – All You Need to Know About Bypassing, Including BGAs Speaker: Robert Hanson, Americom Seminars 3- DAY TECH N I CA L CONF E RE NCE PROGRA M The 3-Day Technical Conference consists of 28 two-hour workshops (W courses) and half-day seminars (S courses) on Monday, September 15, Wednesday, September 17 and Thursday, September 18. Tuesday, September 16 is “FREE Tuesday,” a special day that provides attendees with a variety of complimentary special events and sessions, and plenty of time to visit the exhibition. The short technical courses that make up the 3-Day Techical Conference are included on the Proceedings CD-ROM provided to all conference attendees. MONDAY, SEPT. 15 9 am – 11 am NEW! W1 – Choosing Components for Lead-Free (High-Temperature) Soldering Speaker: Vern Solberg, consultant In compliance with RoHS, suppliers have quietly abandoned all alloy terminal plating that contains lead. Although most companies supplying ﬁnished electronic products to consumers in North America are not required by legislation to comply with RoHS, many are being forced to modify their assembly process. This is because some alloys plated on lead-free components and PCBs are not really compatible with lead-bearing materials. The other issue is the components originally developed for eutectic soldering cannot be used in a lead-free process due primarily to the mold compound’s lack of capability to hold up at the elevated temperatures required for lead-free soldering. Attendees of this two-hour workshop will study and discuss potential impacts of lead-free components, review a number of component manufacturers’ speciﬁcations, consider a number of compatible PCB surface ﬁnishes and better understand the assembly process variables for lead-free solder compositions currently in use. The newly published IPC-7550 standards that guide regulatory and market developments within the electronics industry will be reviewed. ﬁlled with practical and ﬁnancial hazards. Remove some of the mystery by hearing the answers to the most common questions asked by circuit designers and program buyers regarding ﬂex circuits. Culled from a combined 50 years of experience in the industry, the speakers offer a “place to start” when looking for a ﬂex design solution. 1 pm – 3 pm NEW! W3 – Which Lead-Free Solder Works Best? Speaker: Jasbir Bath, Flextronics The electronic manufacturing industry and various consortia continue to believe that the Sn -(34%)/Ag/-(0.5-0.7%)/Cu (tin/silver/copper) alloy composition range (commonly abbreviated as SAC 305/405 alloys) will be the most widely used alloys for surface-mount solder paste in the near future. However, there is an increased and accelerated interest in several different tin-copper based alloys with additions of elements such as silver, nickel, germanium, cobalt, antimony and bismuth for lead-free wave soldering based on technical and commercial reasons. This reduction of silver content (as compared to SAC 305/405) has signiﬁcant impacts in a high-solder volume consumption area such as wave soldering, where the limited supply of silver is a greater concern as compared to surface-mount reﬂow paste. While recognizing that the development of newer alloys is necessary for scientiﬁc and commercial progress, this two-hour workshop highlights concerns with the proliferation of lead-free wave solder alloys into mainstream production. 9 am – 12:30 pm NEW! S1 – Traces as Transmission Lines Speaker: Ralph Morrison, consultant This half-day seminar on traces as transmission lines will cover characteristic impedance, trace geometries, rise and fall times, dielectrics, characteristic impedance control, matching impedances, critical lengths, reﬂections, mismatches, stubs, cross coupling, forward and reverse coupled waves, energy transport, the power time constant, energy management, capacitors as transmission lines, capacitor design problems, and energy storage on ICs. 9 am – 12:30 pm NEW! S2 – Designing Out Common Failure Mechanisms Speaker: Jim Hall, ITM Consulting During the course of assembly process audits and troubleshooting work, trends are see in the types of errors and problems that occur. The resulting process problems wreak havoc with an impact on assembly yields ranging from 5 to 20%. This half-day seminar will cover common lead-free failure mechanisms and identify the “deadly sins” of surface-mount assembly, both for lead-free and “leaded” processes. We will look at feedback methodologies, DFM and assembly design issues, solder paste selection, documentation, and stencil design and tooling. 1:30 pm – 5 pm NEW! S3 – Design for High-Density Surface Mount and Microelectronics Speaker: Vern Solberg, consultant This half-day seminar will look at current IC packaging methodology, packaging standards, review qualiﬁcation requirements, and study land pattern geometry alternatives and circuit routing guidelines, as well as important factors related to high-density PCB fabrication and assembly technologies. Topics covered 9 am – 11 am NEW! W2 – Top 10 Flex Circuit Questions (and Answers) Speakers: Mark A. Verbrugge and Mark Finstad, Minco Products The world of ﬂex circuits is an often confusing place Early Bird Discount Deadline | Re g i ste r b y Au g u st 1 9 a n d sa v e u p to $ 1 0 0 !

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - July 2008

Printed Circuit Design & Fab - July 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.