Printed Circuit Design & Fab - August 2008 - (Page 28) Co-Design Innovative Modeling Supports Co-DeSIgn of the Power SuPPly ChaIn, Part 2 New software tools ease problems associated with power delivery design in large computer systems. by DaviD Quint and Charles Keen AC impedance is a very useful metric from the PDS perspective. It is generally obtained by placing a current source or array of current sources at the die interface in the package and then measuring the AC voltage magnitude as the frequency of the sources is swept across a large range. Dividing the voltage by the current gives an equivalent impedance, Z(f). This impedance will typically display one or more resonances, caused by the inductances and bypass capacitances in the system. During current transients, this can cause ringing of the supply voltage, and the possibility of exceeding the low or high limits of voltage specifications. Recently, a lot of attention has been focused on reduction of this resonance behavior, including usage of dissipative bypass capacitors and multiple sizing of capacitors on the package and board. Figure 5 illustrates such a resonance in an early version of a package design. The Z(f) plot reveals the resonance at a number of locations within the package, which has bypass capacitors mounted at 20 locations surrounding the die. Figure 6 shows the same package, except the arrangement of several different capacitances serves to break up the resonance and reduce its peak impact. Despite the usefulness of the Z(f) plot, it leaves many questions unanswered. In Figure 6, the resonance peak is reduced 28 five times, but the magnitude of the impedance in other frequency regions increased. Depending on the spectrum of the current draw by the die, this could be a worse situation than before. Even if we can obtain a frequency plot of the total voltage response produced by the die, there may be variations across the face of the IC. The AC response of the PDS provides very valuable information, but more is needed. We must have a transient simulation, and we may need information on the voltage drop at critical locations across the die. Transient Step Current This technique is a favorite of power system designers everywhere. It basically provides information that is equivalent or at least similar to the AC ! analysis. The Fourier transform of the step response could be used to create the frequency sweep and vice versa. The step response can be applied more directly to the power draw behavior of a real IC or a system of packaged ICs and can be more meaningful to engineers that deal with transient simulations on a daily basis. It is also easier to specify as a performance metric of a given part. For example, Figure 7 shows the response of the package model to a step in total current (80% to 100% in 3 nS for one of the power domains. The data show the initial DC voltage before the step, followed by a steep drop immediately after the step; then a ringing at two different frequencies and an exponential damping characteristic. ! Figure 5. Simulation showing a resonance at 52 MHz, measured at several nodes within the package. Note the peak magnitude (at L1 center, topmost trace) of 5.6 Ohms. Figure 6. The same package as mentioned in Figure 5, except package bypass caps of three different values have been used to detune and reduce the peak impedance. Note the magnitude (at L1 center, top-most trace) of 1 Ohm. AUGUST 2008 PRINTED CIRCUIT DESIGN & FAB
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - August 2008 Printed Circuit Design & Fab - July 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Software Performance Interconnect Strategies Final Finish Forum Product Development Challenges in a Global Market Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 Low-Loss Fluoropolymer Copper Clad Laminate Qualifying PCBs Outsourced in Asia Copper Plating and Microvia Fill for Advanced PCBs Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - August 2008 Printed Circuit Design & Fab - August 2008 - Printed Circuit Design & Fab - July 2008 (Page Cover1) Printed Circuit Design & Fab - August 2008 - Printed Circuit Design & Fab - July 2008 (Page Cover2) Printed Circuit Design & Fab - August 2008 - Printed Circuit Design & Fab - July 2008 (Page 1) Printed Circuit Design & Fab - August 2008 - Contents (Page 2) Printed Circuit Design & Fab - August 2008 - Contents (Page 3) Printed Circuit Design & Fab - August 2008 - Our Line (Page 4) Printed Circuit Design & Fab - August 2008 - Our Line (Page 5) Printed Circuit Design & Fab - August 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - August 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - August 2008 - Around the World (Page 8) Printed Circuit Design & Fab - August 2008 - Around the World (Page 9) Printed Circuit Design & Fab - August 2008 - Around the World (Page 10) Printed Circuit Design & Fab - August 2008 - Around the World (Page 11) Printed Circuit Design & Fab - August 2008 - Happenings (Page 12) Printed Circuit Design & Fab - August 2008 - Happenings (Page 13) Printed Circuit Design & Fab - August 2008 - ROI (Page 14) Printed Circuit Design & Fab - August 2008 - ROI (Page 15) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page 16) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W1) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W2) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W3) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W4) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W5) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W6) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W7) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W8) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W9) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W10) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W11) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W12) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W13) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W14) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W15) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page W16) Printed Circuit Design & Fab - August 2008 - Tip Jar (Page 17) Printed Circuit Design & Fab - August 2008 - Software Performance (Page 18) Printed Circuit Design & Fab - August 2008 - Software Performance (Page 19) Printed Circuit Design & Fab - August 2008 - Interconnect Strategies (Page 20) Printed Circuit Design & Fab - August 2008 - Interconnect Strategies (Page 21) Printed Circuit Design & Fab - August 2008 - Interconnect Strategies (Page 22) Printed Circuit Design & Fab - August 2008 - Final Finish Forum (Page 23) Printed Circuit Design & Fab - August 2008 - Product Development Challenges in a Global Market (Page 24) Printed Circuit Design & Fab - August 2008 - Product Development Challenges in a Global Market (Page 25) Printed Circuit Design & Fab - August 2008 - Product Development Challenges in a Global Market (Page 26) Printed Circuit Design & Fab - August 2008 - Product Development Challenges in a Global Market (Page 27) Printed Circuit Design & Fab - August 2008 - Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 (Page 28) Printed Circuit Design & Fab - August 2008 - Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 (Page 29) Printed Circuit Design & Fab - August 2008 - Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 (Page 30) Printed Circuit Design & Fab - August 2008 - Low-Loss Fluoropolymer Copper Clad Laminate (Page 31) Printed Circuit Design & Fab - August 2008 - Low-Loss Fluoropolymer Copper Clad Laminate (Page 32) Printed Circuit Design & Fab - August 2008 - Low-Loss Fluoropolymer Copper Clad Laminate (Page 33) Printed Circuit Design & Fab - August 2008 - Low-Loss Fluoropolymer Copper Clad Laminate (Page 34) Printed Circuit Design & Fab - August 2008 - Low-Loss Fluoropolymer Copper Clad Laminate (Page 35) Printed Circuit Design & Fab - August 2008 - Qualifying PCBs Outsourced in Asia (Page 36) Printed Circuit Design & Fab - August 2008 - Qualifying PCBs Outsourced in Asia (Page 37) Printed Circuit Design & Fab - August 2008 - Qualifying PCBs Outsourced in Asia (Page 38) Printed Circuit Design & Fab - August 2008 - Qualifying PCBs Outsourced in Asia (Page 39) Printed Circuit Design & Fab - August 2008 - Copper Plating and Microvia Fill for Advanced PCBs (Page 40) Printed Circuit Design & Fab - August 2008 - Copper Plating and Microvia Fill for Advanced PCBs (Page 41) Printed Circuit Design & Fab - August 2008 - Copper Plating and Microvia Fill for Advanced PCBs (Page 42) Printed Circuit Design & Fab - August 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - August 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - August 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - August 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - August 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - August 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - August 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - August 2008 - BGA Bulletin (Page Cover4)
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