Printed Circuit Design & Fab - August 2008 - (Page 29)

co-dESiGn Ringing frequencies can be estimated from the plot by measuring periods. The ringing frequency usually agrees with the package resonant frequency and its Q factor observed in the AC sweep discussed in the previous section. This analysis includes actual currents that are expected at the IC and provides instantaneous voltage information. When the first versions of the IC model are available, two states of the circuit are extracted: 1) an idle current with no traffic, and 2) a max traffic current where the die is working at full capacity. Presumably, the circuit will make this transition quickly and quite frequently. The initial droop (such as the droop to 1120 mV in Figure 7) reveals the limitation of the on-die capacitance to respond to current changes. Between the die and the first package bypass capacitance is an inductance that will limit the dI/dt, causing the voltage droop that you see. The only cures for this droop are to reduce the package inductance, increase the on-die capacitance or reduce the dI/ dt drawn by the IC. Since the PDS is a linear system, in this simulation, the same amount of overshoot will occur when the load is reduced from full load to 80% of load. The damping effect on the ringing is brought about by several effects, including the ESR (equivalent series resistance) of the bypass capacitors, the resistance of the package materials and the finite resistance of the IC circuitry itself. The real circuit is not a current source but rather a resistor that varies its resistance to change the current that it draws. This type of simulation should use a programmed resistor rather than a current source to draw the measured currents. In this way, the damping effect of the circuit itself is included. In some instances, the magnitude or the slew rate of the transient may not be known, and several variations of this simulation may need to be performed. The current step simulation is specific enough to develop specifications for the component parts of a power delivery system and how they function together. The voltage droop in Figure 7 is one example where the synergy of the IC and package designs is tested. Extending this idea further, the current crossing the package/ board interface is easily compiled. Manufacturers use the step current specification in their part descriptions quite frequently, since it is valuable information for the system designer. The board power designer can place a current source in his model at the location of the part and proceed with the analysis. fiGurE 8 shows the level 2 package current corresponding to the simulation in Figure 7. The height of the step and the dI/dt of the waveform can be measured easily in the simulation. This information is important in determining the amount and values of the on-board bypass capacitors and the bandwidth required from the VRM. It should also be noted that the waveform exhibits the limitations of this specification: the ringing of the waveform is a consequence of the passive Z(f) of the device and use of a current source ignores that effect. Simulations based upon the current step are usually quite adequate if they indicate that there are comfortable margins for error. If the system simulation is indicating marginal or unacceptable noise levels, or some parts of the IC are drawing much higher currents, it may be necessary to opt for more elaborate simulations, not ! only to try new design approaches but to also establish confidence that the problem has been fixed. The use of a more descriptive time domain current source is the next step. Killer Virus Transient Simulation Barring full knowledge of the component part for a complete transient active current simulation, this technique uses step current information and knowledge of the resonant frequencies of the PDS to produce a “speculative worst-case” situation for the simulation. If the component part can pass from lowest average current to highest average current at random times, it is possible that it will do so repeatedly at a repetition rate equal to the period of a PDS resonance. In this case, the voltage across the device would buildup over several cycles of such excitation, reaching a maximum peak-to-peak voltage determined by the current step magnitude and the “Q” of the system resonance. The name “killer virus” comes from the concept that an “assassin” software virus could be designed to excite this mode, and possibly kill the operation of a computer system. fiGurE 9 illustrates the PDS oscillation that results from such a “killer” waveform. The killer virus simulation addresses a very limited type of excitation and should be run as many times as necessary to target each resonance of the system. It may easily be the most severe stress that the system would ever encounter; however, it could lead to over-design of the PDS. The actual load may not produce waveforms that fall into this category, so designing to the worst-case situation may not be necessary. For instance, if the worst-case approach does not incur a great deal of cost increase, then the extra safety factor ! fiGurE 7. Transient voltage response with a step current applied at the IC. The bottom trace is the “die center” trace, starting with DC 1167 mv, drooping to 1120 mv. AUGUST 2008 fiGurE 8. Current drawn by the packaged IC at the package/board interface. This is the sum of all currents in the footprint. This is the same simulation as the previous figure. Rise time is slowed by on-package bypass capacitors. ! fiGurE 9. voltage waveform produced by a “killer virus” excitation. Note that the resulting sinusoid grows in amplitude over several periods. printEd circuit dEsign & faB 29

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - August 2008

Printed Circuit Design & Fab - July 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Software Performance Interconnect Strategies Final Finish Forum Product Development Challenges in a Global Market Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 Low-Loss Fluoropolymer Copper Clad Laminate Qualifying PCBs Outsourced in Asia Copper Plating and Microvia Fill for Advanced PCBs Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - August 2008

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