Printed Circuit Design & Fab - August 2008 - (Page 9)

AROUND thE world 3D-TSV, The next revolution LYON, FRANCE – 3-D TSV wafers will be shipped in the millions and have the potential to in BRIEF Mentor Succeeds in Flomerics Bid. Mentor Graphics increased its bid for Flomerics to about $2.43 per share, or $60 million based on outstanding shares to close the deal. The Flomerics board accepted the new offer. The original bid was about $2.07 per share, or about $47 million.The $60 million purchase price rep.1 resents about a 35% premium over the trading price on May 8, the day Mentor made the initial offer. It’s a 17% increase over the initial offer. AT&S Enters Solar Cell Market. AT&S and Solland Solar, a producer of standard and backcontact solar cells, will cooperate in the development of solar cell and solar module technology. The development is targeting increased energy efficiency and reduced costs. The objective is to achieve these advantages by using processes and materials that are presently standard to the PCB industry. The companies will produce a functional prototype that will be verified for mass production. The agreement between AT&S and Solland Solar is solely a development partnership without any equity investments. Fujitsu Moves PCB Manufacturing to T exas. Fujitsu Telecommunications europe (FTeL) has announced that the decision has been finalized to transfer its PCB manufacturing operations to its sister company, Fujitsu Network Communications (FNC) in Richardson, TX. According to a company release, the decision was made because of “the continuing volatility in demand for products in the global telecommunications market. The transfer is scheduled for comple” tion by year-end 2008. Chemical Prices Rise Again. Dow Chemical has reported that, in a continuing attempt to offset increasing costs for energy and raw materials, it will raise the prices of its products again by as much as 25%. This follows the company’s across-the-board price increases of as high as 20% that were implemented June 1. Dow will also reportedly add a freight surcharge for its North American customers of $300 for shipments by truck and $600 for shipments by rail. In addition, the company will reduce or idle production at some manufacturing plants and will implement cost-cutting measures at its automotive plants in both the U.S. and overseas. Singapore Electronics Growing. Singapore’s electronics industry rose in June, reversing a one-month fall into recession. The sector rose 2.3 points to 51.7 according to purchasing exec, utives in more than 150 industrial companies. May was the first time in nearly two years the electronics sector failed to grow. The national purchasing managers’ index rose 1.6 points sequentially to 50.6 in June, on new orders and higher levels of production output. electronics makes up one-third of Singapore’s manufacturing output. impact as much as 25% of the memory business by 2015, says a new research report. Excluding memory devices, Yole Developpement’s latest market forecast reveals 3-D TSV wafers could account for more than 6% of the total semiconductor industry by 2015. Meanwhile, the equipment market for 3-D TSV manufacturing tools will rapidly expand to above $1 billion by 2013. The research firm says consolidation is taking place in CMOS wafer fabs with a shift toward a fabless foundry model. A new infrastructure needs to be developed in the middle segment of the semiconductor industry supply chain, Yole says. New technologies, equipment and advanced materials coming from the front- and back-end worlds are being developed and will give rise to a revival of semiconductor packaging and circuit assembly. The impetus for 3-D is clear and has not changed much since the technology was introduced into production for MEMS and CMOS image sensors; it is about achieving smaller form factor with increased package densities to meet bandwidth, RF, power consumption performance improvements and further cost reduction, says the firm. In addition, several players are driven by reliability motivations. WL-CSP CMOS image sensors are poised to leave traditional edge interconnect configurations for “real” 3D-TSV architectures as soon as this year, Yole adds. Vias will be partially or completely filled. Additionally, the number of I/Os will expand to several hundreds of interconnects per chip, with a trend to stack the DSP chips under the image sensor chip itself. MEMS will benefit from 3-D to combine MEMS with ASIC, while wireless SiPs will combine heterogeneous layers together. The market for 3-D stacked memories is imminent and is primarily driven by RAM-based memories; meanwhile, more flash memory will be combined within MCP, PoP/SiP packages, cell phone card-slots and SSDs, according to the firm. The question now is: Who will develop the lowest-cost process and take the risk of the huge initial infrastructure investment required first? Going further, logic-based 3-D SOCs are to set to takeoff in the next two to three years for different applications. This “true” 3-D/IC integration will be achieved through the progressive segregation of several layers; 3-D partitioning of embedded memories, RF, analog and I/Os layers from the logic base chip will be achieved in the most cost-effective manner by reducing overall chip size areas, says Yole. 3-D WLP encapsulation is already in production in CMOS image sensors with vias through the backside of the wafer. It will expand to power amplifier modules as well, says the firm. If via-last will account for a large portion of the market, Yole sees a clear trend toward via-first configurations and smaller via sizes approaching 1-5 µm diameters with 500 to 2000 interconnects per chip. A 3-D interposer module is already in small production for several MEMS applications to combine ASIC and MEMS chips together in a true WLP approach. This technology platform is likely to expand rapidly into many SiP application spaces, says the firm. Several barriers to entry exist for full-scale 3-D IC integration, including test, 3-D EDA design tools, thermal management and 300 mm equipment availability. As contact probe test technologies tend to be more limited with via pad density increasing, they may not scale to future pad dimension pitch shrinks. Moreover, as one portion of the industry is going toward wafer-to-wafer stacking schemes with thin wafers, new requirements are emerging for testing without damage at the wafer level to ensure the electrical functionality of the TSV, RDL and bump pad structures prior to the stacking of each layer. As a consequence of this, many companies are requesting contact-less testing technologies, says Yole. Technology and equipment are being developed for wafer surface inspection, open/ shorts electrical testing and 3-D system-level functionality validation. The landscape is different regarding the availability of 3-D EDA design and thermal management software tools. Yole sees effort in this area; however, the company believes it will be a challenge for the industry to get the tools ready by 2011. The availability of 300-mm 3-D TSV equipment is a question of time, the company says. The first 300-mm tool clusters have been shipped this year for production pilot lines. AUGUST 2008 printEd circuit dEsign & faB 9

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - August 2008

Printed Circuit Design & Fab - July 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Software Performance Interconnect Strategies Final Finish Forum Product Development Challenges in a Global Market Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 Low-Loss Fluoropolymer Copper Clad Laminate Qualifying PCBs Outsourced in Asia Copper Plating and Microvia Fill for Advanced PCBs Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - August 2008

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