Printed Circuit Design & Fab - August 2008 - (Page W14)

3- DAY TECH N I CA L CONF E RE NCE PROGRA M THURSDAY, SEPT. 18 9 am – 11 am NEW! W10 – Signal-Integrity Simulation Crash Course Speaker: Tim Coyle, Signal Consulting Group As complexity increases with every new design, the need to simulate an interface to identify acceptable routing topologies becomes even more apparent. While the prospect of setting up a signal-integrity simulation environment can be daunting, with the right understanding of the fundamentals, an interface can be simulated with minimal effort. For PCB designers who are not familiar with setting up a signal-integrity simulation, this two-hour workshop will address the basic building blocks of a signal-integrity simulation that will allow for successful prototyping. A sample DDR3 interface in a DIMM conﬁguration will be used to show the progression of setting up a simulation environment and ﬁnding a solution space for a design parameter. at upcoming issues and challenges to our industry and others. 9 am – 12:30 pm S11 – PCB Layout Guidelines for Signal Integrity, EMI and High Speed Speaker: Susy Webb, Fairﬁeld Industries This half-day seminar will provide guidelines for designers to incorporate the complex physics and electronics behind signal integrity, EMI and highspeed design into actual board design. We will start with electronics basics and why understanding the concepts is important for board layout. We will then discuss incorporating signal integrity and EMI issues into successful board designs. Last, we will illustrate good practices for high-speed board design including placement, stackup, planes, routing and more. 1:30 pm – 5 pm NEW! S13 – A PCB Designer’s Guide to IBIS Models Speaker: Tim Coyle, Signal Consulting Group Simulating a PCB design gives a board designer insight into potential signal integrity issues such as overshoot and setup/hold margin. Using IBIS models to represent the I/O device is a common industry practice to allow fast simulations and is widely supported by most PCB environments and chip vendors. This half-day seminar will cover the basics of IBIS modeling from what they model to how they are generated. We will also discuss how to validate an IBIS model and some tips and tricks to ﬁxing poor quality IBIS models. This will teach designers basic theory behind IBIS models, the process to generate an IBIS model and how to ﬁx an IBIS model. 9 am – 12:30 pm S12 – Predictive Analysis for ThroughHole to HDI Conversion Speaker: Gary Ferrari, FTG Circuits Designers are often faced with the challenge to estimate how many conductive layers a particular board design would require. We use our best experiences to come up with an estimate, but it’s only an estimate. How many times have we run out of routing channels only to have to add an additional layer pair? It worsens if we have to continue adding layer pairs until the design is complete, and it becomes a complete disaster if we have to resort to HDI at the end to complete the project. This halfday seminar looks at variables that are analyzed to predict routing requirements of a design, as well as alternative HDI structures. Design rules, performance gains and cost comparisons highlight this session. The attendee should gain a clear understanding of what critical identiﬁers will lead them to an HDI design, which is a more cost effective alternative than adding additional layers to a current through-hole design, as well as the improved performance gained. 1:30 pm – 5 pm S14 – New Test Methods For HighSpeed, High-Density PCBs Speaker: Robert Hanson, Americom Seminars Due to high-speed, stackup restrictions, blind/buried vias and many other limitations, traditional test methods may not provide the capabilities to test today’s high-speed, high-frequency PCBs. This half-day seminar will explain why traditional test methods – i.e., clamshell ﬁxtures for bare board testing to detect opens/shorts, MDA and ICT for fault detection/fault isolation on the production line and functional test using rack and stack hardware at the operational level – are losing applicability. This course also will deﬁne new methods of test that confront the restrictions and, in turn, provide cost-effective solutions. Attendees will learn much more, including: What is microsectioning testing and what will it accomplish when testing blind and buried vias? Why is vision testing (AOI, X-ray, laser) becoming more popular for testing blind vias? Why is ﬂying probe (F/P) and vision being used at receiving/inspection (R/I)? What test strategies dictate using either test at R/I? How do we use new F/P techniques in lieu of TDR or VNA? How do we conduct Zo test at bare board using TDR or VNA? How do we test when the via/pad can’t be contacted using traditional ICT/MDA BON techniques? What is bead probe testing, and why is it the hottest topic for an emerging new test strategy? 9 am – 11 am NEW! W11 – Bringing Order to the FPGA I/O Planning Madness Speaker: Bruce Riggins, Taray With their zero NRE (non-recurring engineering) and shorter design cycles, FPGAs are increasingly replacing ASICs in mainstream products. Higher pin densities leads to increased routing congestion as more and more signals converge into a smaller and smaller space on the PCB. Design teams struggle with effectively choosing I/O pin assignments that not only work well for the FPGA but that are optimized for the PCB routing. Lacking sufﬁcient EDA commercial tools to deal with the issue, many companies attempt to roll their own solutions. This twohour workshop will present a solution to the FPGA I/O assignment crisis, describing ways of viewing the FPGA design-in effort from a system-level perspective. We will discuss why moving the PCB layout process earlier in the design cycle is imperative and show the beneﬁts that this approach brings. We will also talk about the need to consider the problem from a physical, electrical and logical standpoint. Finally, we will consider the schematic and ECO processes and propose superior solutions and alternatives to dealing with the difﬁculties caused by FPGA pin assignment changes. 1:30 pm – 3:30 pm W12 – Materials for High-Speed, HighFrequency and Lead-Free PCBs Speaker: Rick Hartley, L-3 Communications, Avionics Systems In a high-speed or high-frequency circuit, performance is dependent upon a number of characteristics and variables, which all accumulate to affect the noise budget of the circuit. Several of these issues are driven by the PCB’s base material characteristics. At high frequencies, materials can and do have a profound impact on performance. This two-hour workshop will discuss the base materials commonly used in high-speed digital and highfrequency analog circuits (including FR4), looking at their advantages and disadvantages. It will also detail how to calculate their impact on circuit performance, hence how to choose a cost-effective material for any speciﬁc application. Finally, we will also look at how each of these materials ﬁts into today’s lead-free products. 9 am – 12:30 pm NEW! S10 – Global Environmental Regulations: Updates on RoHS and WEEE, and an Intro to REACH Speaker: Michael Kirschner, Design Chain Associates RoHS and WEEE in the European Union are both going through review cycles, and we’re in the midst of the ﬁrst major compliance activities for REACH (Registration, Evaluation, Authorization, and Restriction of Chemicals). This half-day seminar will provide you with an update on RoHS and WEEE, then spend the bulk of the time on REACH. We will describe what it is, how it impacts electrical and electronic products and supply chains, and what companies need to do to comply as well as identify and mitigate risk. We will also take a look 1:30 pm – 5 pm S15 – The Fabrication Process: A HandsOn Experience for Designers Speaker: Gary Ferrari, FTG Circuits PCBs have evolved over the years into quite complex components utilizing blind and buried vias, embedded components, impedance, etc. A daunting set of design rules is associated with these advances. However, to fully understand and utilize these new requirements, the modern PCB designer must grasp the basics, or foundation, of the processes used to fabricate a high-tech PCB. This highly interactive half-day seminar will cover the basic manufacturing steps while highlighting those areas and the rules associated with them of most concern to the PCB designer. Covered processes include double sided, multilayer, HDI, and blind and buried vias to name a few. The attendee should come out of this course with a clear understanding of the overall PCB fabrication process and how it affects the design process. 1:30 pm – 3:30 pm NEW! W13 – BGA Fanout Patterns Speaker: Charles Pfeil, Mentor Graphics Choosing the appropriate fanout patterns for routing BGAs can enable fewer layers and better signal integrity. When using HDI, many options are available for fanout patterns. This two-hour workshop demonstrates different fanout patterns in the context of HDI stackups and how they can be successfully applied on large dense BGAs. PCB W EST 2008 | WWW .PCBWEST. CO M | IN TH E H E AR T OF S I LI C O N VAL L E Y http://www.pcbwest.com

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - August 2008

Printed Circuit Design & Fab - July 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Software Performance Interconnect Strategies Final Finish Forum Product Development Challenges in a Global Market Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 Low-Loss Fluoropolymer Copper Clad Laminate Qualifying PCBs Outsourced in Asia Copper Plating and Microvia Fill for Advanced PCBs Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - August 2008

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