Printed Circuit Design & Fab - November 2008 - (Page 26)

SySTEM ModElinG plane discontinuous as shown in the CoB case) and discontinuities are all contributive. Loss is a critical factor for both propagation and crosstalk. All metal that has excited or induced current impressed upon it will be susceptible to ohmic loss. The loss will also increase with frequency (skin effect) and with the vicinity of other metal (proximity effect). Every dielectric material also has an associated loss, related to the imaginary part of its electrical permittivity, which will increase with frequency to the point where it may even become dominant in the GHz range. As the number, type and functionality of wireless components, systems and protocols has increased, the need for minimizing through-the-air EM interference has also increased– whether through the demands of regulatory bodies such as the FCC (EMC or electromagnetic compatibility) or by actual interference-causing, self-interference or cross-interference with other systems (EMI or electromagnetic interference). Along with SI and PI, the need to also account for EMI is achieving critical levels. EMI mechanisms of radiation are represented by green arrows. Top-layers of chip, bond wires, package layers and traces are all potentially strong sources of EMI. This is particularly true if systems are either not designed to have differential excitation and ports (which tend to have low radiation due to cancellation of fields) or have excessive asymmetry resulting in common mode generation even under differential design (tends to happen due to a variety of geometrical effects including boundaries, voids, path lengths, impedance profiles and mismatches, non-parallel paths, etc.). Edge effects are created by abrupt boundaries and may give rise to impedance mismatches (critical in power integrity), reflections (critical in signal integrity) and radiation (critical in EMI). It is important that these effects also be modeled accurately. The gray-white arrows show some examples; external boundaries of chips, packages and PCBs cause edge effects. Boundaries of metal planes within these structures also give rise to the same effect. Abrupt edges of material layers, such as the epoxy layer shown, can also cause edge effects. Importantly, internal discontinuities within planes, such as large slots or separate power planes, also yield strong edge effects. These effects can range from fringe capacitance through impedance mismatches to radiation, and they need to be accounted for in generating models for SI, PI or EMI. We may be approaching a limit on the clock frequencies of individual digital cores. With the advent of multi-core systems and the mushrooming of mixed-signal, analog and RF systems at multi-gigahertz frequencies, the throughput of signals through these systems is continually on the rise. The ever-increasing speed and frequencies of chip-packageboard-systems, unfortunately, has a deleterious effect on the electromagnetic scenario. Practically every EM phenomenon gets more involved as frequencies and speeds increase. Skin effect forces current to travel through smaller cross-sections and rapidly increases the loss and resistance with frequency. Dimensions of geometries become electrically larger as frequencies increase, and more sections of the system become efficient radiators, thereby increasing EMI, crosstalk and radiation loss. Simple approximations, such as transmission line models, transverse EM (TEM) models and lumped models, also become drastically inaccurate. Dielectric materials start behaving in an increasingly lossy and frequency-dependent manner, causing signal distortion and loss through dispersion and attenuation. Even for power integrity applications, with power signals near DC, switching effects on multi-GHz frequency rise times are now common and necessitate highfrequency modeling even for PI problems. It is clear that SIPI-EMI is moving into the arena where full-wave, 3D electromagnetic modeling is a necessity and simpler, more efficient approximations are becoming irrelevant. Designers need to be aware that such approximations may produce results that have no basis in reality for design or verification. Electromagnetic Modeling Approaches 3D Resistance extraction. This entails the solution of either a resistive network problem involving digital chip layers or modeling substrate losses. While this requires modeling of full 3D geometry, it is a relatively simple computation. 3D RC extraction. The next level of complexity involves creating 3D RC models for chip metal layers and substrates, obtained by solving Poisson’s equation. The models are suitable for timing and delay computations and for on-chip signal integrity and power distribution networks at relatively low clock frequencies. 3D RLC extraction. On-chip modeling at GHz frequencies necessitates the modeling of inductance in addition to RC modeling. The potentially distributed nature of inductance loops, as well as frequency dependence due to skin and proximity effects, makes this a significantly more involved problem, but very relevant for on-chip modeling. 3D Quasi-Static Modeling. This technique of modeling has at one end RLC modeling at the package level. In a more complex version, the R, L and C are coupled and derived from the same solution. The phase term (occurring in Green’s functions) is ignored during full-wave modeling. Physically, this is equivalent to assuming all influences (currents, voltages, fields) travel instantaneously through the system. NOVEMBER 2008 Propagation effects Crosstalk effects EMI effects Edge effects FiGurE 2. Depiction of sample of sample electromagnetic effects Figure 2: Depiction electromagnetic effects. 26 printEd CirCuit dESign & fAB

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Printed Circuit Design & Fab - November 2008 Contents Our Line Market Watch Around the World Happenings ROI Positive Plating Ten Tips to Improve Manufacturability 3D Chip-Package-Board Modeling Improving Circuit Simulation With The Addition Of Real Measurements Ad Index PCB West: Interview with NBS Design Inc. The Influence of Final Finish on Lead-Free Assembly Reliability The Lead-free Soldering Challenges for Peelable Resists Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - November 2008

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