Printed Circuit Design & Fab - November 2008 - (Page 28)

SySTEM ModElinG Quasi-static models are widespread for full-port electrical models for packages. These typically have validity up to the low GHz range and are used for both power integrity and signal integrity. 2D transmission Line Modeling. This is traditionally a very useful technique when there are significant symmetries and structures present in the problem. For example, well-designed parallel PCB traces over a ground plane can be modeled very well with per-unit-length (2D cross section) RLGC parameters. These have restricted validity for more general propagation paths and need book-keeping and corrections when traces pass over voids, bend, connect to vias, change their width, have impedance discontinuities, etc. This technique primarily focuses on differentially excited, symmetric structures. 2.5DteM Approximations. When electromagnetic fields are localized to flow between parallel metallic plates with small gaps relative to wavelength, transverse electromagnetic approximations are valid. Such an approach is termed to be of 2.5 dimensions and has been used successfully, primarily for power integrity modeling. 2.5D Layered Approximations. For on-chip RF, analog and mixed-signal components such as embedded passives (filters, inductors, transformers, etc), the relative sizes of the components are small when compared to the lateral extent of the dielectric layers. In this case, layered infinite (in transverse directions) approximations make the solution efficient and accurate, and 2.5D-layered method-of-moments techniques can be used. This also has applicability on some subsets of PCB modeling, but it is generally inapplicable there and on packages where 3D edge effects are important. 3D Full-Wave Modeling. This represents the most accurate approach to EM modeling of chip-package-boardsystems. There are significant challenges to achieving this goal in terms of scale, memory and time while preserving the expected accuracy of 3D full-wave modeling. There are three main techniques that are considered to be the workhorses of this area, and most successful commercial solvers are built around highly efficient versions of these techniques. The finite element method (FEM), initially used in civil engineering, is a staple of 3D full-wave modeling. It is a general technique that uses volumetric meshes to convert the partial differential equation (PDE) form of Maxwell’s equations in the frequency domain to a large, sparse matrix equation. Challenges of Inputs to eM Solvers. Chip-packageboard-system models need to be prepared for analysis by EM solvers. This typically means integrating several different file formats. Net identification, port definition and boundary condition specification (especially in FEM and FDTD where this is not automatic) are also needed prior to solution. Challenges of Outputs from eM Solvers. Even with complex EM solvers that may solve part of or the entire simulation problem, the appropriate outputs are critical. In particular, S-parameter, impedance or admittance matrices are useful to understand propagation and coupling in systems. However, for circuit-level simulation, circuit models need to be generated from these matrices. These models need to be passive and causal in order to ensure that the circuit outputs 28 are accurate and stable. Impedance profiles and time-domain reflection/transmission plots are also required. Recent Advances Advances in computing platforms, coupled with recent breakthrough in algorithms, have dramatically changed the picture in 3D EM simulation for chip-package-board-system co-design. In particular, MoM techniques, that typically were restricted to 2.5D-layered solvers, have recently become extremely powerful due to advanced multi-scale algorithms. These techniques accelerate the iterative solution of MoM matrices by replacing the quadratic cost of matrix-vector products with near-linear costs in the size of the system matrix–which in turn is dependent on the number of mesh elements. This linear scaling, in terms of solution time and memory, is particularly attractive for large structures such as integrated chip-package-board-systems. In addition, these multi-scale algorithms are also amenable to parallelization on shared memory systems; the entire matrix-vector product is parallelized over multicore CPUs. These three techniques will continue to be the mainstay of 3D EM simulation for chip-package-board-systems. Emerging Needs and Future Directions With rapid advances in solver technology, focus is now shifting towards true design tools. These tools will enable fast parametric simulation in a large number of parameters enabling what-if analysis and early design. Tunable accuracy and precision will also enable early design optimization. As systems continue to be designed at the edge of technological capabilities, manufacturing tolerances and design for manufacturing (DfM) will be critical at all levels of hierarchy. Statistical modeling, mean-variance and higher-order variability measures, probability distributions and yield estimates will all be critical– both in a standalone manner and in the context of robust optimization. Optimization will rely on multiple objectives and multiple parameters, requiring extremely efficient solvers as well as visualization and graphing techniques. Eventually, advances in computing languages will allow the development of more flexible-solver architectures that will determine the most efficient simulation method for a specified accuracy or a subset of the entire problem. These needs and directions are sure to keep designers, design automation tool developers and researchers in excited and busy for years to come. pCd&f dr. VikraM Jandhyala is CeO and founder of Physware, Inc. He is also an associate professor in the department of electrical engineering, University of Washington, Seattle and director of the applied computational engineering lab there. He can be reached at vj@u.washington.edu. dr. diPanJan GoPE is VP of research and development, dr. FEnG linG is VP of engineering, dr. xirEn wanG is a research and development engineer, dr. SwaGato chakraBorty is the VP of products, dEVan williaMS is a senior research and development engineer and JaMES PinGEnot is a senior research and development engineer, all working for Physware, Inc. NOVEMBER 2008 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - November 2008

Printed Circuit Design & Fab - November 2008 Contents Our Line Market Watch Around the World Happenings ROI Positive Plating Ten Tips to Improve Manufacturability 3D Chip-Package-Board Modeling Improving Circuit Simulation With The Addition Of Real Measurements Ad Index PCB West: Interview with NBS Design Inc. The Influence of Final Finish on Lead-Free Assembly Reliability The Lead-free Soldering Challenges for Peelable Resists Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - November 2008

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