Printed Circuit Design & Fab - November 2008 - (Page 39)

LEAD-FREE rEliaBility cracking of boards was observed in all finished boards for drop testing. In the bend test, this type of failure was typically observed in OSP and ImAg types of boards after 5000 cycles. This mechanical fatigue failure can be correlated with slow deformation failure and also with the conventional fatigue model. The localized stiffening of the PCB and the overall high strength of lead-free solder component could have contributed to the board failures. Interconnect failure under drop impact loading occurs mainly in the interface region and is determined by the properties of the intermetallic layers. In the drop test, the results that are observed in this study contradict some of the results in other studies4,5. Also, it has been well documented that Ni-Sn intermetallics are less forgiving than Cu-Sn intermetallics, which predict longer characteristic life for OSP and ImAg boards as compared to ENIG boards. Some of the reasons could be early copper trace failures or voids. Quantitatively, a high number of voids were observed for ImAg finished assemblies. ImAg has a tendency to form oxides at reflow temperature, and when organics evaporate and get trapped in molten solder, they could form the unexpected micro-voids. better under thermal stresses compared to mechanical shock type stresses. Also, some products may require more than one PCB surface finish: one for solderability and another for electrical contacts that experience some level of mechanical abrasion. One example of this would be the use of a selective OSP finish for solderability and a nickel-gold finish where electrical contacts are involved. Thus, a plurality of PCB surface finishes is not uncommon in modern day portable electronic products. The interpretation of reliability data can also be complex in portable electronic products, especially when we include drop test stress testing. Solder joints, as well as PCB trace failures, can be observed. It is difficult to discern which failure occurred first since only electrical continuity is monitored and failure analysis is done at the end of the testing. Data are fitted to a statistical distribution without regard to a specific failure mechanism. PCB trace failures are dependent on the card structure and specific mechanical properties. Card thickness, number of layers in the multilayer board, trace characteristics and the nature of trace entry to the pad each have an effect. It becomes important that test vehicles closely match and mimic the product cards. Even then, differences in results, some times conflicting, cannot be ruled out. The failure mechanisms and the reliability characteristics are dependent on the particular board and package characteristics and also on the component locations on the PCB. A comparison of reliability results from different studies can be difficult unless there is a high degree of commonality among such aspects as components, test cards, assembly processes, test parameters and failure criteria. It is important for the designer be aware of all the variables involved in the proper and judicious choice of the PCB final finishes. pCd&f acknowlEdGMEntS the authors thank Fahad Zahedi, Steve Dunford and Robert Darveaux from Amkor for helping to acquire the test boards, components and the facility for assembling the hardware. Authors also thank tommi Reinikainen and Juscelino Okura at the Nokia Institute of technology (INdt) in Manaus, Brazil, for their valuable advice and funding. this work was done at Department of Mechanical engineering at the University of texas at Arlington and does not neccessarily represent an endorsement by Intel Corporation. rEFErEncES FIGURE 3c. PCB solder joint interface with I 1. JeDeC JeSD22-B111, Board Level Drop test Method of Components for Handheld, electronic Products, July 2003. 2. Hossain M.M., Zahedi F Lakhkar N.R., Viswa., nadham P Dunford S.O. and Agonafer D., “ ., Reliability of tin-Silver-Copper solder interconnects under mechanical loading with different PWB finishes, Proceedings of surface ” mount technology international conference, 2008, Orlando FL. 3. tee,t Ng, H.S., Lim, C.t Pck, e., and Zhong, .y., ., Z., “Board Level Drop test and Simulation of tFBGA Packages for telecommunication Applications, the Proc. of the 53th Ieee/eIA ” electronic Components and technology Conference, 2003. 4. lai y.S., yang P . and yeh C.L, “ experimental .F studies of board level reliability of chip-scale package subjected to JeDeC drop test condition, Journal of Microelectronics reliability ” No. 46, pgs 645-650, 2006. 5. Zhu W.H., Xu L., Pang J.H.L, Zhang X.R., Poh e., Sun y.F Anthony y.S.S., Wang C.K. and tan ., H.B. “ Drop reliability study of PBGA assemblies with SAC305, SAC105 and SAC105Ni solder ball on Cu-OSP and eNIG surface finish, Proceedings of electronic Components ” and technology Conference, Orlando FL. Conclusion Reliability of solder interconnections plated with three different surface finishes was examined for two different mechanical loading situations. The choice of PCB surface finishes depends on a number of factors, and it is important to consider all of them prior to product prototype build. The first consideration is the product use environment followed by reliability requirements. Some finishes may perform better in mechanical shock environments than others, while some may perform FIGURE 4a. Cracked part in cyclic bend test. FIGURE 3c. PCB solder joint interface with ImAg. FiGurE 4a. Cracked part in cyclic bend test. NOVEMBER 2008 FIGURE 4a. Cracked part in cyclic bend test. FiGurE 4B. Cracking of board after impact drop testing. MohaMMad hoSSain, Ph.D, quality and reliability engineer, Q&R AtD Intel Corporation; nikhil lakhkar, Ph.D candidate, Department of Mechanical engineering, the University of texas at Arlington nikhil. lakhkar@uta.edu; ViSwanadhaM PuliGandla, Ph.D, adjunct faculty, Department of Mechanical engineering the University of texas at Arlington; dErEJE aGonaFEr, Ph.D, professor, Department of Mechanical engineering the University of texas at Arlington. FIGURE 4b. Cracking of board in impact drop test. printEd CirCuit dESign & fAB 39

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - November 2008

Printed Circuit Design & Fab - November 2008 Contents Our Line Market Watch Around the World Happenings ROI Positive Plating Ten Tips to Improve Manufacturability 3D Chip-Package-Board Modeling Improving Circuit Simulation With The Addition Of Real Measurements Ad Index PCB West: Interview with NBS Design Inc. The Influence of Final Finish on Lead-Free Assembly Reliability The Lead-free Soldering Challenges for Peelable Resists Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - November 2008

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