Printed Circuit Design & Fab - November 2008 - (Page 48)

BGA 0.8-mm Pin Pitch BGAs, Part 3 Any-layer vias can be stacked to span any set of layers. tHIS ARtICLe FOCUSeS on the use of any-layervias in which the micro-vias traverse only two layers individually; however, they can be CHArlES stacked to span any pfEil set of layers including starting on the top and ending on the bottom of the board. It is my belief that this general methodology will increase in popularity quickly and will eventually become the predominant via model for all PCBs. A footprint for a Virtex-5 with 1760 pins (1227 I/Os) at 1-mm pitch was converted to 0.8-mm pitch as the basis for the tests. This test uses an any-layer-via stackup in which every layer is buildup and has a via-hole in it. Via spans are created by continuous coincident locations up and down the stackup. There are different design rules used in this test because it is expected that when any-layer-vias (FiGurE 1) are widely adopted, the fabrication process will have gone through another miniaturization cycle. This stack-up allows vias to span any set of consecutive layers. The any-layer-via provides a unique opportunity to try different patterns. The pad is small and only exists on the layer-pairs that are needed. In FiGurE 2, each ball pad connected to ground uses a thermal relief and a via that goes to the bottom side of the board. These vias are embedded in the plane and are located near each ground ball pad. The holes for the ground and power vias are larger than the vias for the signals to ensure adequate current carrying capacity. The vias are aligned in a diagonal at the corners. This provides additional routing space as you can see in FiGurE 3. FiGurE 1. Any-layer-via stack-up. FiGurE 3. Layer 2 corner via patterns and breakouts. In Figure 3, all the 1:2 fanout vias that are connected on this layer do not need to extend to Layer 3. The ground and power vias extend layer-by-layer all the way through the board. Shifting the vias into a diagonal, horizontal or vertical alignment has maximized the route density. In FiGurE 4, all the 1:2 vias do not exist on Layer 3. This leaves a tremendous amount to room for routing. In FiGurE 5, the vias in the center area of the BGA are aligned either vertically or horizontally, and diagonally in the corners. This fanout pattern again uses the basic principle of swinging the vias to align them into columns. Remember that if through-vias are used, then only one trace can fit between the arrays of vias under the BGA. The power and ground vias have a slightly larger diameter than the signal vias and, therefore, make the routing space between the columns of vias a little smaller. In this case, however, the space is not compromised enough to reduce the route density. Using the any-layer-vias increases the amount of route space significantly, as it traverses down each layer. On Layer 3, the entire outside perimeter of the BGA is wide open, with only the vias for power and ground appearing. Continued on p. 35 FiGurE 2. top layer ground plane detail without net class colors. 48 FiGurE 4. Layer 3 corner via patterns and breakouts. FiGurE 5. Layer 1 center via patterns (test 3). NOVEMBER 2008 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - November 2008

Printed Circuit Design & Fab - November 2008 Contents Our Line Market Watch Around the World Happenings ROI Positive Plating Ten Tips to Improve Manufacturability 3D Chip-Package-Board Modeling Improving Circuit Simulation With The Addition Of Real Measurements Ad Index PCB West: Interview with NBS Design Inc. The Influence of Final Finish on Lead-Free Assembly Reliability The Lead-free Soldering Challenges for Peelable Resists Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - November 2008

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