Printed Circuit Design & Fab - December 2008 - (Page 18)

PCB Stackup analysis and Design, Part 2 Stackup analysis can help to optimize layer count, trace width and spacing and electrical performance. WHeN DeSIGNING a PCB stackup, it is essential to consider requirements. Depicted by FiGurE 4 are two single-ended traces having line width W, thickness t, edge-to-edge separation Sn and height over reference plane H. Er is the relative dielectric constant of the substrate. dr. ABE In order to minimize crosstalk, it (ABBAS) riAzi is desirable to set H as small and Sn as large as allowed by board target impedance and routing restrictions.14 The effect of these stackup parameters on crosstalk15 is disclosed by Equation 1 (FiGurE 5). Lm is mutual inductance between two neighboring wires, H equals the thickness of the dielectric substrate and L is the line inductance. The center-to-center spacing (s) and edge-to-edge spacing (Sn) for two traces of width W are directly related as shown by Equation 2 (Figure 5). Crosstalk requirements control trace separation (pitch), which in turn influences board density and the number of routing layers. From Equations 1 and 2, it follows that crosstalk noise (between two neighboring traces) being proportional to mutual inductance, decreases as Sn increases or H decreases. Optimizing trace separation is also valuable for controlling crosstalk between two coupled differential pairs, as illustrated in FiGurE 6. Crosstalk between differential pairs 1 and 2 can be diminished by widening Sn. A study of far-end crosstalk (FEXT) and crosstalk-induced jitter involving two edgecoupled differential pairs of W = 5 mil and interapair separation Sp = 5 mil, revealed that increasing the pairto-pair spacing Sn from 5 mils to 20 mils can significantly reduce FEXT16 and deterministic jitter (DJ). Other measures to avoid crosstalk problems include minimizing parallel run lengths, incorporating guard traces15 and orthogonally routing the signal lines which belong to adjacent routing layers. crosstalk1 To attain good signal integrity, a clean15 unobstructed return path is demanded for high-speed signals. Signal and power quality degradation can occur in PCBs and IC packages due to high-speed traces traversing17 planesplits. Plane layers fulfill several duties in power distribution networks (PDNs). They can transfer DC current from source to load, connect bypass capacitors to active components and furnish a return path18 for the signals. Current flows on power distribution in a manner to diminish total impedance.19 At low frequencies, this translates to minimizing resistance by spreading20 over every possible path. At high frequencies, the return current crowds under the signal (on reference plane) to minimize inductance. It is important to avoid splits on ground or power planes, but there are situations when it is inevitable.20 For instance, power islands and moats arise when multiple powers are incorporated on the same plane. Sometimes, it is necessary to allow a plane layer cut-out beneath a connector21 in order to lessen the mounting pad capacitance. Under such circumstances, when cutouts on reference planes are unavoidable, it is critical not to route highspeed buses over such voids (unless the plane with slots is sandwiched between two uniform/continuous planes). The return current path is also interrupted whenever a signal transitions from one layer to another and changes reference planes. It is then desirable to place near the signal via22 another via (if both reference planes are of same type) or a decoupling capacitor (if one reference plane is a ground while the other one is power). This FiGurE 4. a two microstrip transmission lines geometry. 18 FiGurE 5. Several formulae related to coupling and impedance. DECEMBER 2008 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - December 2008

Printed Circuit Design & Fab - December 2008 Contents Our Line Market Watch Around the World Happenings ROI Global Sourcing EMC for the Real World Interconnect Strategies On the Forefront Final Finish Forum Test and Inspection Electronic System Design Data Management 101 Designers Take on Technology Challenges in 2008 PCB Signal Integrity, Power Integrity and EMC Challenges What’s in a Name? Ad Index PCB Dielectric Materials for High-Speed Applications Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - December 2008

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