Printed Circuit Design & Fab - December 2008 - (Page 19)

FiGurE 6. Two coupled differential pairs. can furnish for the return current a high-frequency lane between the two reference planes. Thickness of metal (i.e. plane and signal) layers is a significant option when constructing PCB stackup. Thicker cladding offers lower resistance and symbolizes a good selection for power planes19. Thinner cladding sustains narrow lines with superior width control; hence, thin cladding is often a logical preference for signal layers to achieve high density routing. Utilizing 0.5 oz copper for signal layers is a good choice for impedance control3 since only a very small amount of etching is necessary to produce a trace. This allows controlling the trace width to within +/- 0.5 mils. However, there are also cases in which thicker traces are desired in order to decrease the trace’s DC resistance (or for realizing superior thermal performance), although it is more difficult to attain impedance control for thicker traces. Accomplishing impedance control for high-speed, single-ended signals (such as memory buses and CPU interfaces) and differential pairs (high-speed serial-links, differential clocks, etc.) is vital in stackup design. Mathematical equations exist for calculating single-ended and differential impedance23. These formulas offer useful insight regarding how impedance depends on various stackup parameters (e.g., dielectric constant, trace width, dielectric thickness). For instance, Equation 3 (Figure 5) which is an IPC recommended23 approximation for microstrip impedance, reveals that Zo decreases as the dielectric constant (Er) increases, copper thickness (t) increases or trace width (W) increases. Furthermore, Zo increases as dielectric height H increases. Equation 4 (Figure 5), which applies to edge-coupled DECEMBER 2008 microstrip using FR4 material23, illustrates that differential impedance Zdiff is a function of Zo (the uncoupled single-ended characteristic impedance for each trace), edge-to-edge separation between traces Sn and dielectric thickness H. Impedance formulas can provide helpful insight and more precise results than rules of thumb approximations, but the accuracy of such analytical techniques is usually limited to about 10%. Ascertaining impedance to a higher degree of exactness would require the use of a field solver program. Whenever a PCB undergoes modifications, it is necessary to perform stackup analysis24. Such assessment considers optimum number of layers, board size, routing density, copper weight, power needs, PCB thickness, dielectric materials, trace widths/separation, most favorable impedance, price and manufacturability. Application of HyperLynx Stackup Editor for impedance planning is illustrated by FiGurES 7. The Stackup Editor allows adding or subtracting layers and incorporating soldermask. For each dielectric, it permits selecting technology (prepreg or core), thickness, dielectric constant and loss tangent. For metal layers, it allows defining metal type (for correct resistivity and temperature coefficient). Trace widths and thickness can be specified for each signal layer. The Zo Planning tab allows for specifying target printEd CirCuit dESign & fAB 19 http://www.envisionrules.org http://www.envisionrules.org

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - December 2008

Printed Circuit Design & Fab - December 2008 Contents Our Line Market Watch Around the World Happenings ROI Global Sourcing EMC for the Real World Interconnect Strategies On the Forefront Final Finish Forum Test and Inspection Electronic System Design Data Management 101 Designers Take on Technology Challenges in 2008 PCB Signal Integrity, Power Integrity and EMC Challenges What’s in a Name? Ad Index PCB Dielectric Materials for High-Speed Applications Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - December 2008

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