Printed Circuit Design & Fab - December 2008 - (Page 23)

TEST AND INSPECTION Pushing Test and Testability Up the Chain How a grassroots organization can help get managers on board. eVery COMPaNy always looks to improve their bottom line but I would venture to say that doing so becomes even more important in times of economic turmoil. Cost-cutting is taking on new levels in recent times. In the past few years, companies have embraced defect detection, and StACy even prevention and process control have KAliSz become givens. It is only lately, however, joHnSon that design for test (DfT) and design for testability are becoming prevalent. Defective products not properly tested because they lacked DfT can cut into revenue generation through later time-to-market, recalls, rework, extension of the warranty period and earlier-than-intended product termination.1 As a concept, DfT is not new. I would argue, however, the financial upside of these implementations is only now really being acknowledged. For example, we’ve given lip service over and again to the reduction of warranty return yet new examples of products coming out with huge warranty return rates continue to surface. If companies really begin to embrace DfT and testability concepts, these situations would be avoided or, at the very least, reduced. Let’s explore cost as it is an interesting factor. Let’s say the designer is designing a microprocessor with >1000 pins and choose not to use boundary scan. Then the in-circuit test system will need a >1000 pin bed-of-nails fixture. Let’s say the boundary scan microprocessor was going to be $50 and the non boundary scan was $30. The cost savings is $20 per processor but where does the added complexity from using that >1000 pin fixture and the fixture cost break even? The added cost for the boundary scan processor will pay off (and then some!), but decision makers tend to get caught up with Benefits of DfT DfT benefits include the following2: • Reduces the time required to pass the design into manufacturing • Lowers manufacturing cost • Minimizes the design engineer’s involvement in production setup • Improves cross-functional communication between design, engineering and manufacturing • Lowers both initial and life cycle costs • Decreases test times and virtually eliminates harrowing production delays • Guarantees more efficient diagnosis and repair in the field • Provides more accurate diagnostics to the part initial pricing at the expense of big-picture items such as return over time and return on investment. In fact, this is an issue that faces all test – regardless of quality of the design. Understanding the initial investment will pay off and then some is the concept that every inspection and test supplier is trying to demonstrate all the time. Management teams need to get on board and embrace the long-term gain (shorter time to market, less warranty return, less rework, etc.). This is one of the main goals of the Testability Management Action Group, or TMAG (tmag4dft.org). Its grassroots efforts are targeting management on all levels to get the message out to positively impact future products. From a practical perspective, what can the average test engineer do? As with anything design-related, one of the biggest drivers needs to be collaboration across organizations. I can remember several examples from when I was a process development engineer where a design came my way for build/ test and there were no fiducials on the board, thus eliminating any hope of a robust solder paste or optical inspection. Another example: If a product is designed such that it is to be tested by automated x-ray inspection only, and the designer throws it over the wall to the test group which thought in turn expected an in-circuit implementation, there will be issues that cost money and time. The SMTA (smta.org) has partnered with TMAG and is working on a refreshed Testability Guideline. Be sure that you and your design engineers have a working copy. This will prevent simple mistakes from entering in product designs and will permit standardizations that will reduce design time over time. Within these guidelines you’ll find instructions for keep-outs, clearances, tolerances, carrier recommendations, and so on. In general, be proactive. Partner with your design counterparts. Join TMAG and learn how to approach management to sign on the dotted line. Incorporating design for test and testability will bring things further upstream and will standardize on many aspects, thus making the implementation phase easier and more robust. pCd&f rEFErEncES 1. louis y. Ungar, “The economics of Harm Prevention Through Design for Testability, International Test Conference Proceedings, October 2008. ” 2. Thomas J. Coughlin, “Designing for Testability… The Technology, the Technique, and the economics, July 30, 1996 Web posting, http:// ” members.aol.com/prpca/designof.htm. Stacy kaliSZ JohnSon is americas marketing development manager at agilent (agilent.com); stacy_johnson@agilent. com. DECEMBER 2008 printEd CirCuit dESign & fAB 23 http://www.tmag4dft.org http://www.smta.org http://members.aol.com/prpca/designof.htm http://members.aol.com/prpca/designof.htm http://www.agilent.com

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - December 2008

Printed Circuit Design & Fab - December 2008 Contents Our Line Market Watch Around the World Happenings ROI Global Sourcing EMC for the Real World Interconnect Strategies On the Forefront Final Finish Forum Test and Inspection Electronic System Design Data Management 101 Designers Take on Technology Challenges in 2008 PCB Signal Integrity, Power Integrity and EMC Challenges What’s in a Name? Ad Index PCB Dielectric Materials for High-Speed Applications Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - December 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.