Printed Circuit Design & Fab - December 2008 - (Page 36)

SySTEM dESiGn routing, with a low level of signal ringing. In multi-layer routing for a bus structure of four or eight nets, the SSN condition of all drivers switching at the same time demonstrates increased skew and increased ringing as the bus width increases. Net lengths were intentionally kept short to avoid proximity coupling effects. The results are unchanged for circuit analysis if this circuit-level effect is intentionally ignored in the hybrid analysis. Circuit analysis ignores PI effects and, for all cases, predicts exactly the same rise time degradation and maximum overshoot as for the ideal single-net, single-layer case. FiGurE 5 shows the transient voltage at the receiver load of SSN condition for the multi-layer bus with eight drivers. The black reference trace for single-net, single-layer routing and the violet trace for the bus are duplicated from FIGURE 4. The addition of four, large-valued, 0805 capacitors yields the yellow curve. The skew is eliminated and the maximum overshoot is reduced from a completely unacceptable level of 772 mV to a better, but still troublesome, 260 mV. The addition of two, smaller-valued, 0603 decoupling capacitors local to the two via transition regions yields the red trace. Maximum overshoot is dramatically reduced to 49 mV, just 10 mV higher than the ideal case of single-net, single-layer routing. The implicit global ground applied precludes PI effects; therefore, decoupling capacitors are not included in circuit analysis. A semi-numerical and approximate analysis technique can be implemented to apply circuit analysis techniques by gridding power/ground planes and representing local RLC parasitics for each grid point. However, this approximate PI analysis cannot include signal nets. 3D EM analysis of this simple example could be performed without reaching computational capacity limits. Though nearly identical analysis results are achieved by 3D EM and hybrid analysis for these simple designs, the computational resources of hybrid analysis are >100 times less for time and memory. Relationship of SI and PI to EMC SI issues result in reflections and ringing on signal nets. Signal nets exposed to the top or bottom of the board without power plane shielding can leak energy. Nets with global extent, long interconnects and significant reflection result in higher emission levels. Synchronous signals, such as clocks, and SSN conditions on buses also present potential EMC challenges due to the current flowing in the nets. However, signal net current cannot exist in the absence of return current in the power planes; therefore, emissions from signal current flow are only part of the EMC challenge. Local return current changes for multi-layer vias and signal nets that cross voids in planes can result in emissions usually much lower than the more global power radiated current changes due to noise voltage at power plane edges. Multi-layer via transitions, net crossings of split-planes and SSN bus conditions all cause power plane noise. Minimizing these physical structures and careful decoupling capacitor placement lowers power plane emissions. In practice, power plane emissions typically dominate PCB emissions; less often, synchronous clocks (especially their higher harmonics) dominate. Emissions cannot be characterized from PCB geometry alone, as they are critically dependent on currents in the nets and noise voltage on power plane edges. Thus, system-level analysis must be performed prior to emissions characterization. In this sense, EMC analysis is a post processing step after SI/PI analysis. EMC analysis is primarily a post-layout process. However, significant EMC risk can be eliminated through pre-layout emissions analysis of power planes with their corresponding decoupling capacitor placement and selection. Current source drivers are applied to represent the transient switching profile of devices; a good representation of power plane emission levels is predictable very early in the PCB design process. FiGurE 4. SSN without decoupling capacitors. FiGurE 3. PCB trace and bus routing alternatives: top layer only or involving both top and bottom layers. 36 FiGurE 5. The effects of decoupling capacitors for multi-layer bus routing. DECEMBER 2008 printEd CirCuit dESign & fAB

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Printed Circuit Design & Fab - December 2008 Contents Our Line Market Watch Around the World Happenings ROI Global Sourcing EMC for the Real World Interconnect Strategies On the Forefront Final Finish Forum Test and Inspection Electronic System Design Data Management 101 Designers Take on Technology Challenges in 2008 PCB Signal Integrity, Power Integrity and EMC Challenges What’s in a Name? Ad Index PCB Dielectric Materials for High-Speed Applications Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - December 2008

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