Printed Circuit Design & Fab - January 2009 - (Page 48)

BGA Looking Forward PCB footprints for mobile chipsets. ALtHOUGH I AM considered an expert in my field, and I am welllearned in many other areas, in the context of all possible knowledge, my CHARlES ignorance is still PFEIl infinite. With technology, there are so many avenues to pursue that we gladly rely upon others to walk the unknown paths. Our combined observations, insights and creativity magically result in progress towards faster, cheaper and better products with a goal to lift the standard of living for all mankind — at least from my optimistic point of view. Researching BGA routing challenges has been an interesting endeavor and communicating my discoveries has allowed me the privilege of knowing that I, too, have made some small contribution to the advancement of PCB design. What pleases me even more is meeting people in this industry who tell me of their ideas, struggles and successes in their own pursuits. During the past year, I have spent much of my time with PCB designers discussing the challenges of routing large dense BGAs. At the beginning of the year, when addressing an audience, I would ask two questions: how many used BGAs with over 1500 pins; and how many were either using High Density Interconnect (HDI) or evaluating it. A year ago, the results were along the lines of 20% and 25% respectively. During the past few months, the response has risen to about 30% and 75%. Although my ad hoc polling is of no scientific value, the results are in line with some trends I have observed during my meetings with designers. The movement to HDI fabrication has increased significantly, driven primarily by the mobile and handheld market and, more importantly, due to the use of fine-pitch BGAs, meant for the mobile market, on other products. What appears to be driving the adoption of HDI is not the 1500-pin to 2000-pin BGA at 1.0 mm pin-pitch; but rather, it is the 400-pin to 600-pin BGA at 0.6 mm pin-pitch or smaller. Often, I speak of a threshold that will force these designs into HDI. This threshold will be crossed when the 0.8mm pitch BGA with 2000 pins arrives and multiple instances are required on one design, for example, on network cards or emulation cards. Using drilled through-vias will not be practical because it will result in too many layers. This threshold has not been crossed yet. Large pin-count FPGAs and ASICs are still being packaged with a 1.0-mm pitch. While the large pin-count packages have remained relatively stable, the finepitch (<0.8mm) BGAs with over 400 pins have arrived this year and are causing trouble for PCB designers. Most of the questions I get are along the lines of, “I have this 500-pin BGA with a 0.6-mm pitch. What kind of fanout pattern can you recommend? Oh, and did I mention we are required to use throughvias?” Invariably, early in the design cycle, someone made a decision to use a fine-pitch BGA meant for a handheld device on a larger computer board. Last month’s BGA Bulletin column is focused on solutions for those situations. I continue to hunt the Internet for new BGA packages. Most recently, Intel has published datasheets for mobile chipsets that include some very interesting ball patterns. FiGurES 1, 2 and 3 illustrate the PCB footprints I made for those devices. PCD&F charlES PFEil is an engineering director for Mentor Graphics, Systems Design Division. Email: charles_pfeil@ mentor.com. At www.mentor.com/go/ bga you can obtain a copy of Charles’ book, “BGA Breakouts & Routing” . FiGurE 1. Illustrates a pattern for Intel ICH9m-SSF Package referenced in the Intel I/O Controller Hub 9 (ICH9) Family with 569 pins. the ball pads on the inner section are on a 0.65-mm pitch and the outer five rows are on a 0.6-mm pitch. 48 FiGurE 2. Shows a ball pattern for Intel Micro FCBGA Package with 956 pins. this pattern has a pitch of 0.952 mm between ball pads on the same row and with the alternating pattern, 0.476 row to row. FiGurE 3. Shows a ball pattern for Intel Mobile 4 Express Series Package with 1329 pins with a mix of 0.7-mm and 0.8mm pin pitch. the three perimeter rows can use 1 to 2 or 1 to 3 microvias, the 10 to 12 paired columns can use buried or through-vias with plenty of room for routing differential pairs. the center is reserved for power and ground. JANUARY 2009 PRINTED CIRCUIT DESIGN & FAB http://www.mentor.com/go/bga http://www.mentor.com/go/bga

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - January 2009

Printed Circuit Design & Fab - January 2009 Contents Our Line Market Watch Around the World Happenings ROI The Signal Doctor Positive Plating Final Finish Forum Making Sense of Laminate Dielectric Properties Design and Fab Tips for Improving Solder Mask Registration Automating the DDRx Interface Verification Process Printed Circuit Design & Fab Annual Buyers Guide: Special Suppliers Section Printed Circuit Design & Fab Annual Buyers Guide: Guide to Products and Services Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - January 2009

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.