Printed Circuit Design & Fab - February 2009 - (Page 26)

HS SiMulation Simulation: The Need for Speed Establishing selection criteria can help determine the best simulation model for a specific task. by TIMoTHy CoyLE The jitter specifications for SerDes (Serializer/Deserializer) interfaces keep getting smaller, and the timing margins for memory interfaces, like DDR3, keep shrinking until they are almost gone. As design margins shrink, PCB designers need to be able to predict how designs are going to behave in order to avoid costly re-spins and rework. The goal of any signal integrity simulation is to validate that the interfaces on the PCB design will meet timing and noise margin specifications. By using simulations at the right times in a PCB design flow, costly board spins and rework can be avoided, as illustrated in FiGurE 1. Simulations give the designer a window into what is happening in a system. A typical process flow involves pre-layout and post-layout simulations. At the pre-layout phase, major or minor simulation work can be performed. For new designs, simulations can be used to find the best topology for an interface bus and validate IO buffer characteristics such as drive strength and edge rate. For interfaces, like DDR3 that require a detailed timing analysis to ensure that setup and hold times are met under various conditions, simulations are the only way to achieve that goal. The results of the pre-layout simulations can be used to develop layout rules so the PCB will meet specifications. These layout rules can often be used in a CAD constraint manager tool to help automate the process. For post-layout simulations, the actual board topology and routing are extracted from the CAD database to verify that the interface will work as designed. This phase can be used to validate the layout rules developed in the pre-layout phase. channel loss seen at 5 Gbps, designers are using advanced circuit techniques, like equalization and clock recovery, to open the eye back up at the receiver. Traditional SPICE (Simulation Program with Integrated Circuit Emphasis)-based models do not easily model these advanced techniques, and tools such as Matlab are often used to develop the algorithms to describe these implementations, as shown in FiGurE 2. Modeling formats such as IBIS-AMI (Input/Output Buffer Information Specification - Algorithmic Modeling Interface) have been developed to provide a universal standard to describe these algorithms so that they can be used across EDA tools. Using traditional time-domain SPICE simulations for these SerDes interfaces is FiGurE 1. Signal quality of a signal (1) overshoot (2) ringback (3) settling time (4) non-monotonic edges. New Challenges in SerDes Design Implementing high speed SerDes devices can be complicated and time consuming– especially with new technology standards like PCI Express Generation 2.0 that have frequencies above 5 Gbps. This new wave of SerDes devices presents challenges to simulating and measuring a design. To compensate for the 26 FiGurE 2. SerDes Channel Diagram. FEBRUARY 2009 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - February 2009

Printed Circuit Design & Fab - February 2009 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar BGA Bulletin Interconnect Strategies Final Finsh Forum Defects Database Embedded Active Components In Multilayer LCP Packages Simulation: The Need for Speed Advanced Registration Systems The DC Design Squeeze Ad Index Do You Really Want a Better Autorouter? Designing With Conductive Materials, Part 1 Off th eShelf Marketplace On the Forefront

Printed Circuit Design & Fab - February 2009

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