Printed Circuit Design & Fab - February 2009 - (Page 27)

HS SiMulation FiGurE 4. Block diagram of an IBIS IO buffer. FiGurE 3. Simulation models become more complicated as frequencies increase. vendors offer proprietary solutions for embedded instrumentation, and there is movement among various organizations that set industry standards to add support. Memory Interfaces Require Detailed Analysis no longer feasible, as the bit error rate requires simulating millions of bits. This has brought on a new wave of statistical eye diagram methods to simulate long bit error rates in a relatively short amount of time. This statistical analysis uses the channel’s impulse response to compute the eye statistics. Measuring the actual eye at the receiver provides challenges as well because the circuit equalizations often happen inside the receiver and not at the package pin where most measurements are taken. Traditional scan chain and JTAG methods, used to test PCB designs at these frequencies, no longer work. Many are moving towards embedded instrumentation which provides the ability to view the internal signals after equalization has occurred. Some silicon In the past, traditional parallel interfaces often have taken a back seat to the more complicated SerDes interfaces, but with the introduction of DDR2/3, things are starting to change. With future DDR4 interfaces targeting 2667 MHz frequencies, parallel interfaces soon will have some of the same issues as SerDes designs. However, parallel interfaces like DDR2/3 have their own challenges that require simulation to ensure the design will work. The major challenge with a memory interface like DDR3 is making sure the layout and routing of the interface meets the stringent setup and hold timing requirements. After taking into account the different types of skew and loss seen in a memory bus, the remaining timing margin might measure only tens of Chat Us UP Stop by Virtual PCB this month and get chatting! Join chats on new environmental regulations, HDI design and processing, laminates, SMT processing, test and inspection, and defect prevention. Led by industry experts like Happy Holden and Charles Pfeil of Mentor Graphics; Dr. Mike Bixenman of Kyzen; Ken Parker of Agilent Technologies; Chrys Shea of Shea Engineering; Mike Kirschner of Design Chain Associates; Phil Zarrow of ITM Consulting; Dr. David Bernard of Dage and Dr. Jane Feng of Flextronics. Listen to the experts talk – even join in if you wish. All at the industry’s only virtual trade show! For information on the chats, visit virtual-pcb.com/attendees/#chats. For information on attending or exhibiting at Virtual PCB, visit virtual-pcb.com. FEBRUARY 2009 printEd CirCuit dESign & fAB 27 http://www.virtual-pcb.com http://www.virtual-pcb.com/attendees/#chats http://www.virtual-pcb.com

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - February 2009

Printed Circuit Design & Fab - February 2009 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar BGA Bulletin Interconnect Strategies Final Finsh Forum Defects Database Embedded Active Components In Multilayer LCP Packages Simulation: The Need for Speed Advanced Registration Systems The DC Design Squeeze Ad Index Do You Really Want a Better Autorouter? Designing With Conductive Materials, Part 1 Off th eShelf Marketplace On the Forefront

Printed Circuit Design & Fab - February 2009

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