Printed Circuit Design & Fab - February 2009 - (Page 34)

SiMulation The dC deSigN Squeeze DC simulations can help meet tight voltage margins and avoid field failure risk. by LESLIE LANDERS and TANIT VIRUTCHAPUNT The power handling capacity for IC package and printed circuit board structures is a major design challenge and a critical factor for successful product implementation. The trend to pack more performance onto chips has necessitated operating with higher current at lower voltage levels. Under- and over-voltage conditions impact end-product performance and reliability, making DC analysis an important requirement for PCB and package design flows. Supplying a constant two volts to a chip was fairly straightforward when the required current was 40 amps, but those days are long gone. Today, voltage tolerances are razor thin challenging designers to meet 5% or less of nominal operating voltage. Marketplace realities exacerbate the challenge. Those with tight schedules, fixed end product price points and constrained physical dimensions can not simply add copper and layers. Going forward, difficulties will only increase. As seen in FiGurE 1, clock rates and current loads are rising at the same time chip voltage levels and feature sizes are declin- ing. The International Technology Roadmap for Semiconductors (ITRS)1 points to challenges across diverse chip product lines from high-end microprocessor to consumer portable devices. While the pressure for processing speed will accelerate, there is an upper bound on available power. On-chip Data Processing Engines (DPEs) have rising power appetites that can outstrip package sourcing and dissipation limits, and mobile devices are limited by the imperative to conserve battery life. According to the ITRS Roadmap, current package power limits will be exceeded by 4x by 2020, resulting in a forced reduction of chip content and logic activity. IR Drop Delivering reliable power to circuits is always of critical importance because DC drops can happen at every level in a chip, package and board system.2 Components that are distant from their associated power source are particularly susceptible to IR drop, and designs that rely on battery power must minimize voltage drop to avoid unacceptable power loss. From a board design point of view, component supplier datasheets provide a valuable reference and guide for the total margin of both DC IR drop and AC noise. For the end product to function as anticipated, power fluctuations must remain within datasheet tolerances. Traditionally, design teams have used a ratio of 80:20 for AC noise / IR drop. The higher percentage of the margin allocated for AC is necessary because issues associated with noise can be particularly difficult to mitigate. Still, the resulting squeeze on the DC budget increases the headaches associated with assuring overall power efficiency, reliability and performance. The good news is that when designers pay close attention to DC performance, they are rewarded with an additional cushion for managing AC noise, as depicted in FiGurE 2. FEBRUARY 2009 FiGurE 1. ITRS Roadmap trends point to challenges for designers. 34 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - February 2009

Printed Circuit Design & Fab - February 2009 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar BGA Bulletin Interconnect Strategies Final Finsh Forum Defects Database Embedded Active Components In Multilayer LCP Packages Simulation: The Need for Speed Advanced Registration Systems The DC Design Squeeze Ad Index Do You Really Want a Better Autorouter? Designing With Conductive Materials, Part 1 Off th eShelf Marketplace On the Forefront

Printed Circuit Design & Fab - February 2009

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